Aayush Bhattacharya — Software Engineer
I am a physical design engineer currently working at Synopsys, specializing in building low-power and high‑performance chips at advanced technology nodes from 7nm down to 2nm. I have a proven track record in delivering high quality results across topics like PnR, floorplanning, STA, EMIR, formal verification, and physical verification. Utilised Tools include: Fusion Compiler PrimeTime Redhawk-SC Formality Calibre and IC Validator
Stackforce AI infers this person is a semiconductor design engineer specializing in physical design for advanced technology nodes.
Location: Hyderabad, Telangana, India
Experience: 4 yrs
Skills
- Physical Verification
- Design Rule Checking (drc)
Career Highlights
- Expert in low-power, high-performance chip design.
- Proven track record in physical design methodologies.
- Specialized in advanced technology nodes from 7nm to 2nm.
Work Experience
Synopsys Inc
ASIC Physical Design Staff Engineer (1 mo)
ASIC Physical Design Senior Engineer (2 yrs 4 mos)
ASIC Physical Design Engineer - 1 (1 yr 7 mos)
Graduate Engineering Trainee (5 mos)
Education
Master of Technology - MTech at Indian Institute of Technology, Madras
Bachelor of Technology - BTech at National Institute of Technology Warangal
Class XII at Step By Step High School, Jaipur
Class X at Step By Step High School, Jaipur
