Swarnima Jain

DevOps Engineer

Faridabad, Haryana, India7 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Branch Topper in B.Tech
  • Secured STAR of APEEJAY award
  • Scholar badges for 6 consecutive years
Stackforce AI infers this person is a VLSI design engineer with expertise in verification methodologies.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)Synopsys Tools

Other Skills

SystemVerilogVerilogCadence XceliumShell ScriptingVHDLVery-Large-Scale Integration (VLSI)CPerlUNIXMicrosoft OfficeMicrosoft ExcelMicrosoft WordMicrosoft PowerPointManagementELDO

About

CAREER OBJECTIVE >To secure a challenging position which provides me the opportunity to tap my full potential professionally and personally, enhancing my abilities to become a valued asset to the organisation. ACHIEVEMENTS >Branch Topper in B.Tech (till date) >Secured STAR of APEEJAY award in class 12th >School Topper in PCM-MMWT in class 12th >Secured SATYA PAUL award in high school >Secured scholarbadges for 6 consecutive years

Experience

7 yrs 6 mos
Total Experience
2 yrs 6 mos
Average Tenure
4 yrs 1 mo
Current Experience

Synopsys inc

VIP RnD Engineer ll

May 2022 – Present · 4 yrs 1 mo · Noida, Uttar Pradesh, India

Synopsys toolsUniversal Verification Methodology (UVM)

Cadence design systems

Product Validation Engineer 1

Jul 2019 – May 2022 · 2 yrs 10 mos · Noida Area, India

Stmicroelectronics

Intern

Jun 2018 – Jan 2019 · 7 mos

Education

YMCA University of Science & Technology

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jan 2015 – Jan 2019

Apeejay School Faridabad

12th

Jan 2014 – Jan 2015

Apeejay School Faridabad

10th

Jan 2012 – Jan 2013

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