Aneek Jash

Software Engineer

Bengaluru, Karnataka, India2 yrs 10 mos experience

Key Highlights

  • Expert in standard cell design and dynamic simulations.
  • Strong background in RFIC and RF design.
  • Proficient in functional verification and cell characterization.
Stackforce AI infers this person is a VLSI design engineer with expertise in RFIC and digital circuit design.

Contact

LinkedIn

Skills

Core Skills

Standard Cell DesignDynamic Simulation

Other Skills

Cadence VirtuosoCell CharacterizationCustom IP DesignDigital IC DesignFunctional VerificationIntegrated Circuits (IC)PrimelibRF DesignRTL DesignRV SimulationsRadio Frequency (RF)Radio Frequency Integrated Circuit (RFIC)VerilogVery-Large-Scale Integration (VLSI)

Experience

2 yrs 10 mos
Total Experience
2 yrs 10 mos
Average Tenure
2 yrs 10 mos
Current Experience

Intel corporation

Circuit Design Engineer

Aug 2023 – Present · 2 yrs 10 mos · Bengaluru, Karnataka, India

  • Standard Cell design, dynamic simulations, functional checks and characterization. Custom IP design for metal R/C correlation btw pdk and silicon. RV simulations on cells/block.
Standard Cell DesignDynamic SimulationFunctional VerificationCell CharacterizationCustom IP DesignRV Simulations

Education

Indian Institute of Technology, Delhi

M.Tech — RFDT

Jan 2021 – Jan 2023

National Institute of Technology Durgapur

B.Tech — Electronics & Communication Engineering

Jul 2017 – May 2021

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