Anik Saha — Software Engineer

Experienced Technical Lead having 12+ years of industrial experience in ASIC/SOC Physical design. - Have worked in designs of Chips related to mobile processors, Servers, Graphic Controllers and Automotive industries. - Worked on designs with Low Power and multiple STA modes. - Hands-on experience with blocks, sub-systems, and SoCs from Synthesis to GDSII in technology nodes ranging from 4nm, 5nm, 7nm, 16nm, 28nm, 40nm, and 65nm. - Skilled in Floorplanning, pin placement, and sub-block partitioning - from the Data Flow model. - PnR (Congestion Analysis, Debugging and Resolutions). - CTS (Un-clocked flops debugging, Skew balancing, and Latency Reduction), clock early and late strategies, and Routing. - STA - Constraints development and refining (Functional and Test modes), Timing Closure (tool-based and Manual ECO generation). - Synthesis (Logical and Physical) using DC, DCT and DC-SPG. - Actively involved in grooming of 1-3 years experienced candidates. - Strong technical expertise with an M.Tech in Microelectronics from Birla Institute of Technology and Science, Pilani and a B.Tech in Electronics and Communication Engineering (ECE) from Techno India, WBUT, Kolkata TECHNICAL EXPERTISE: • Physical Design Flow (PnR, CTS, Route), STA, Synthesis DC-SPG • Tools: Cadence Innovus, Synopsys ICC, ICC2, Prime Time (PTSI), Design compiler (DC/DCT/DC-SPG), • Good Knowledge of the ASIC/SOC design flow • Good experience in Static Timing Analysis and Timing Closure (Manual ECO generation) • Scripting: Tcl, dbGet commands, awk

Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in ASIC and SoC physical design.

Location: South Delhi, Delhi, India

Experience: 15 yrs

Skills

Physical Design
Asic Design
Soc Design
Automotive Design
Static Timing Analysis
Dft
Testing

Career Highlights

12+ years in ASIC/SOC Physical Design.
Expertise in low power and multiple STA modes.
Strong mentoring experience for junior engineers.

Work Experience

Synopsys Inc

Sr Staff Engineer (2 yrs 1 mo)

Qualcomm

Senior Lead Engineer (3 yrs 5 mos)

SpicaWorks

Physical Design Lead Engineer (1 yr 9 mos)

UST Global

Senior Techical Analyst (Physical Design) (1 yr 10 mos)

SmartPlay Technologies - An Aricent Company

Senior Physical Design Engineer (2 yrs 4 mos)

Wipro Limited

Physical Design Engineer (1 yr 8 mos)

VLSI ENGINEER (DFT) (2 yrs 1 mo)

Education

Master's Degree at Birla Institute of Technology and Science, Pilani

Bachelor's Degree at West Bengal University of Technology, Kolkata

High School at D.A.V Public School, DELHI

Anik Saha

Software Engineer

South Delhi, Delhi, India15 yrs experience

Highly Stable

Key Highlights

12+ years in ASIC/SOC Physical Design.
Expertise in low power and multiple STA modes.
Strong mentoring experience for junior engineers.

Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in ASIC and SoC physical design.

Contact

Skills

Core Skills

Physical DesignAsic DesignSoc DesignAutomotive DesignStatic Timing AnalysisDftTesting

Other Skills

MacrosClock DistributionP&RInnovusFloorplanningSynthesisGDSIIClock Tree SynthesisDRCLVSSTAECO GenerationScan InsertionJTAGATPG

About

Experience

15 yrs

Total Experience

2 yrs 7 mos

Average Tenure

2 yrs 1 mo

Current Experience

Synopsys inc

Sr Staff Engineer

May 2024 – Present · 2 yrs 1 mo · Noida, Uttar Pradesh, India · On-site

Qualcomm

Senior Lead Engineer

Dec 2020 – May 2024 · 3 yrs 5 mos · Noida, Uttar Pradesh, India

MacrosClock DistributionP&RInnovusFloorplanningPhysical Design+1

Spicaworks

Physical Design Lead Engineer

Mar 2019 – Dec 2020 · 1 yr 9 mos · Noida Area, India

Responsible for Synthesis to GDSII of SoC level implementation.
Hands on experience of tool-sets from both Synopsys and Cadence- Design Complier (DC, DC-SPG), ICC/ICC2, Innovus, Formality, VCLP and Primetime (PTSI).
Extensively worked on developing and refining both functional and test mode constraints.
Clock tree synthesis (reducing clock latency and skew balancing).
Timing closure activities included timing ECO generation (both tool based and manual).
Worked on SoC level IO Interfaces (SDIO, SQIO, ethernet).
Actively involved in grooming of 1-3 years experienced candidates.

MacrosClock DistributionP&RFloorplanningSynthesisGDSII+2

Ust global

Senior Techical Analyst (Physical Design)

May 2017 – Mar 2019 · 1 yr 10 mos · Noida Area, India

Senior Physical Design Engineer, responsible for Synthesis to GDSII deliveries of Sub-system designs.
Good exposure to Automotive blocks and sub-systems of 16nm technology node.
In-depth exposure to Floorplan activities for Automotive chips keeping in mind the FP requirements from MBIST and LBIST perspective.
Well versed in dealing with congestion issues, analysis and resolution at Placement stage.
Sound knowledge of CTS (latency reduction and skew balancing) and routing.
Timing Signoff (ECO cycles) and PV closure (DRC, LVS, IR-drop, EM resolutions).
Tools: DC, DCT, DC-SPG, ICC2, Formality, PT-SI.

MacrosClock DistributionP&RFloorplanningDRCLVS+2

Smartplay technologies - an aricent company

Senior Physical Design Engineer

Jan 2015 – May 2017 · 2 yrs 4 mos · Noida Area, India

Worked as Physical Design and STA Engineer.
STA timing closure signoff activities.
Tweaker based ECO generation
Manual Timing ECO generation for DRV closure (trans, cap, fan-out splitting and cloning).
Good hand-on in manual setup and hold fixes generation.
Noise/Glitch fixing ECOs.

MacrosClock DistributionSTAECO GenerationPhysical DesignStatic Timing Analysis

Wipro limited

2 roles

Physical Design Engineer

Jul 2013 – Mar 2015 · 1 yr 8 mos

Worked as Physical Design Engineer. Responsible for following PD activities:
Block level implementation from Netlist to GDSII, Technology nodes 28nm, 40nm.
Hands-on experience of Flooplanning, Placement (Congestion Analysis, Debugging and Resolutions)
CTS and Routing.
STA Signoff - Timing Closure
Physical Signoff - DRC (Base, Metal, Antenna), LVS.
Tools: ICC, Primetime-PT, Calibre-DRC/LVS.
Scripting - TCL and PERL

MacrosClock DistributionP&RFloorplanningDRCLVS+2

VLSI ENGINEER (DFT)

Jun 2011 – Jul 2013 · 2 yrs 1 mo

Worked as a DFT Engineer in Wipro Technologies Ltd. Have hands-on experience of DFT in:
Scan Insertion at top and module level
JTAG (IEEE 1149.1) Boundary Scan Insertion and Verification
ATPG Pattern Generation and Verification
Pattern validation and simulation
PERL scripting for reporting and TCL for automating tasks.

Scan InsertionJTAGATPGTCLPERLDFT+1