Arvind Vanam

Director of Engineering

Bengaluru, Karnataka, India14 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Director of GPU IP Integration at Intel Corporation.
Extensive experience in hardware verification and architecture.
Co-founder of a startup focused on IoT solutions.

Stackforce AI infers this person is a semiconductor and IoT expert with strong hardware and software development skills.

Contact

Skills

Core Skills

Hardware VerificationVerification PlanningFirmware DevelopmentSoftware Development

Other Skills

Architecture specificationTest case executionDebuggingFPGA validationTest planningFeature developmentUnit testingCisco TechnologiesGNU DebuggerLAN SwitchingData StructuresPerlClearCaseReal-Time Operating Systems (RTOS)C (Programming Language)

Experience

14 yrs 5 mos

Total Experience

4 yrs 9 mos

Average Tenure

5 yrs 8 mos

Current Experience

Intel corporation

2 roles

Director of Engineering

Promoted

Jul 2025 – Present · 10 mos

Technical Manager

Sep 2020 – Oct 2025 · 5 yrs 1 mo

Bodhileaf

Co-Founder

Nov 2017 – Sep 2020 · 2 yrs 10 mos · Bengaluru, Karnataka, India

Product development for hardware products and IoT solutions

Nvidia

Senior Application Specific Integrated Circuit Engineer

May 2011 – Jun 2017 · 6 yrs 1 mo · Hyderabad Area, India

Hardware verification and minor architecture work for Terga line of chips.
Assumed the role of verification lead for multiple projects for Audio Processing Engine cluster, Security Engine and Backbone cluster at all 3 levels: Unit, cluster and system level.
Following were the roles and responsibilities.
Review project requirement documents
Review system and module Internal Architecture Specification documents with the arch team
Prepare project requirements in terms of man hours required and dependencies for the project
Assign verification resources based on skills required for the project
Prepare verification plans for the modules owned by me and review all verification plan prepared by rest of the team internally and then with Arch, Design and software teams
Execute verification plans by writing/updating test plans, test cases for new features and bugs from previous projects
Create or update testbenches or VIPs as per project requirements
Debug issues and execute/maintain RTL sim /GLS/ X-Prop regressions
Review RTL changes by the design team
FPGA and Silicon validation/Bring up for the modules
Support software team during driver development

Hardware verificationArchitecture specificationVerification planningTest case executionDebuggingFPGA validation+2

Cisco systems

Senior Software Engineer

Aug 2008 – Apr 2011 · 2 yrs 8 mos · Bengaluru, Karnataka, India

Firmware and software Development for following Edge routers:
C10K
BGP PIC EDGE feature: BGP PIC EDGE allows for faster convergence of BGP routes by making the convergence of routes prefix independent.
Multilink Frame Relay to .1q Interworking: Enables interworking between Multilink Frame Relay and .1q and like to like cases of MFR with and without Fragmentation enabled (FRF12)
Punt filter: A debug feature which dumps packets being punted to the Route processor by the forwarding engine based on parameters like IP address, packet size and few others specific to the platform.
ASR 9K
VPDN config development: Development of CLI for VPDN on ASR9k to function as L2TP Access Concentrator. The work involved both cli and xml development for the VPDN configs.
Role and Responsibilities in above Products:
● Feature development as listed for PXF (Forwarding Engine) of C10k and ASR 9k edge routers
● Ownership of components like QOS, Multilink (MLPPP, MLFR), MPLS
And few other components under PXF.
● Unit testing the bug fixed or feature delivered.
● Review the code, functional specs and test plans written by other engineers.
Languages: Microcode (assembly) for NT3PE chip and C
OS: IOS for C10k, IOS-XR for ASR-9k