A

Askari A.

Software Engineer

Greater Toronto Area, Canada0 mo experience

Key Highlights

  • Proficient in Universal Verification Methodology (UVM)
  • Hands-on experience with Assembly Language in firmware development
  • Strong foundation in Computer Engineering from University of Toronto
Stackforce AI infers this person is a skilled ASIC Engineer with a focus on verification methodologies and firmware development.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)

Other Skills

Assembly LanguageVMMReal-Time Operating Systems (RTOS)SystemVerilogLeadershipPython (Programming Language)C (Programming Language)C++

About

-_-

Experience

0 mo
Total Experience
--
Average Tenure
--
Current Experience

Amd

Silicon Design Engineer 2

Mar 2026 – Present · 3 mos · Markham, Ontario, Canada · On-site

Synopsys inc

2 roles

ASIC Digital Design Sr Engineer

May 2025 – Feb 2026 · 9 mos · Markham, Ontario, Canada · Hybrid

ASIC Firmware Engineer intern

Sep 2023 – Aug 2024 · 11 mos · Nepean, Ontario, Canada · Remote

Universal Verification Methodology (UVM)Assembly Language

Education

University of Toronto

Bachelor of Applied Science - BASc — Computer Engineering

Jan 2020 – Jan 2025

Stackforce found 100+ more professionals with Universal Verification Methodology (uvm)

Explore similar profiles based on matching skills and experience

CHANDAN JHA

CHANDAN JHA

Senior Hardware Engineer

at Qualcomm

Bengaluru, India5 yrs 9 mos exp
Physical DesignMicroarchitecture
Srinath Jeevakumar

Srinath Jeevakumar

Senior Architect

at NVIDIA

Bengaluru, India6 yrs 8 mos exp
Performance VerificationSilicon Bring-upPerformance Analysis
Gadireddi Manohar Krishna

Gadireddi Manohar Krishna

Verification Engineer

at Siliciom Technologies Pvt Ltd

Bengaluru, India4 yrs exp
IP VerificationSystemVerilog
SP

Sandeep Prabhakaran

Verification Engineer

at NVIDIA

Sunnyvale, United States2 yrs exp
Verification and Validation (V&V)UVM
Crisil Thomas

Crisil Thomas

Senior Staff Engineer

at Qualcomm

Bengaluru, India11 yrs 1 mo exp
Design VerificationHardware EngineeringCache VerificationPCB DesignFPGA Design
SC

Sandeep Chintala

R&D Engineering, Staff

at Synopsys Inc

Hyderabad, India4 yrs 10 mos exp
System on a Chip (SoC)System VerificationVerification IPSystemVerilog
Andrew Rehkopf

Andrew Rehkopf

ASIC Digital Design, Staff Engineer

at Synopsys Inc

Toronto, Canada0 mo exp
RTL DesignSoC IntegrationVerificationSystemVerilog
HM

Haolin Ma

ASIC Verification Engineer

at AMD

Toronto, Canada2 yrs 11 mos exp
ASIC Digital Design