Chanakya Uppalapu

CEO

Andhra Pradesh, India2 yrs 10 mos experience

Highly Stable

Key Highlights

Expert in Formal Verification and RTL Design.
Hands-on experience with industry-standard tools.
Strong problem-solving and analytical skills.

Stackforce AI infers this person is a Formal Verification Engineer with expertise in semiconductor design and verification.

Contact

Skills

Core Skills

Formal VerificationRtl Design

Other Skills

Problem SolvingVerilogIntel Quartus PrimeCircuitsCoverage AnalysisDFTAutomatic Test Pattern Generation (ATPG)BISTLinuxEDAJiraRTL CodingVery-Large-Scale Integration (VLSI)Functional Verification4G

About

I'm a active learner and good in team work. I would like to work on new challenges there by learn new things that are happening around the industry.

Experience

2 yrs 10 mos

Total Experience

2 yrs 10 mos

Average Tenure

2 yrs 10 mos

Current Experience

Cadence

2 roles

Lead Application Engineer

Jan 2026 – Present · 4 mos · On-site

Senior Application Engineer

Jul 2023 – Present · 2 yrs 10 mos · On-site

Synopsys inc

Formal Verification Engineer

Aug 2022 – Jul 2023 · 11 mos · Bengaluru, Karnataka, India · On-site

In this internship, I have worked as a Formal verification Engineer with hands on writing system Verilog assertions and trained on Synopsys VCFORMAL Industry tool apps such as FPV, FCA, CC and FTA

Problem SolvingVerilogFormal Verification

Maven silicon

Internship Trainee

Jun 2021 – Aug 2021 · 2 mos · India

In this internship program I have worked on RTL design of RISC using VERILOG , I have designed Reduced Instruction Set Computer (32-Instruction Set Architecture) using three stage pipelined structure. The design is verified against standard verification provided by Maven Silicon. During this internship I have learned designing various digital design blocks like Program counter , Register block, Integer file, Decoder ,Machine control ,Store unit and Load unit.

Problem SolvingIntel Quartus PrimeRTL Design