Indu Kumari

Product Engineer

Bhiwani, Haryana, India7 yrs 6 mos experience

Highly Stable

Key Highlights

Over 6 years of expertise in SOC verification.
Led teams in complex verification projects.
Holder of 2 US patents.

Stackforce AI infers this person is a highly skilled ASIC Design Verification Engineer with extensive experience in semiconductor verification.

Contact

Skills

Core Skills

C Based Soc VerificationUniversal Verification Methodology (uvm)Ddr4C (programming Language)

Other Skills

SV and UVM based Subsystem and IP verificationComputer ArchitectureSystemVerilogDigital Signal ProcessorsEthernetPacket CaptureSystemCDFITest PatternGate Level SimulationAutomatic Test Pattern Generation (ATPG)RISC-VAssembly LanguageInterruptsPython

About

Dedicated DV Engineer with over 6 years of professional expertise in C based SOC verification, SV and UVM based Subsystem and IP verification. Collaborated effectively with RTL Design , Physical Design and Product Engineering team members to thoroughly test and verify the DUT for successful tape out, including closure on coverage metrics , GLS and post-silicon validation. Known for my quick-learning abilities, hardworking nature, commitment to excellence, and relentless drive to deliver exceptional and timely results through cohesive team-effort and empathetic leadership.

Experience

7 yrs 6 mos

Total Experience

2 yrs 3 mos

Average Tenure

1 yr 8 mos

Current Experience

Maxlinear

Staff Design Verification Engineer

Nov 2022 – Present · 3 yrs 6 mos · Bengaluru, Karnataka, India · On-site

Frenus Tech Acquired by Maxlinear .
DDR at Subsystem and SoC level Verification :
This included AXI Host VIP , CDN DDR VIP and SNPS DDR controller and PHY and Micron memory model.
Performance monitor to refine the DDR utilization and latency.
Scheduler Block Level Verification :
Led a team for Block level Verification of Scheduler involved scheduling the data from multiple Data Store FIFO to Ethernet ports via uplink and front haul packet processors.
Digital Pre-distortion (DPD) IP in System C TB environment. UVM based DPD Subsystem and SoC level Verification using DPD SYSC Ref model.

Universal Verification Methodology (UVM)Computer ArchitectureSystemVerilogDigital Signal ProcessorsDDR4Ethernet+3

Western digital

2 roles

SOC Design Verification Engineer

Promoted

May 2021 – Nov 2022 · 1 yr 6 mos

On Behalf of Frenus Tech
Verification for SSD controller : Responsible for Verification of Test Controller and Frequency Monitor.
Post Silicon Validation Bring up : Test Pattern Development for Characterization and DFT testing of Silicon Dies. Delivered Modular Patterns which facilitated Core Patterns of the SOC.
Verification for SD/uSD controller : Responsible for Verification of Test Controller , Clock Management Controller(CMC) and Advanced Test Bus(ATB).
From May to Nov 2021 , Worked on IP Design Verification in Frenus Tech :
UVM based Reference model development of RISC V CSR (Control and Status registers) instructions.
C based Verification of Interrupt controller in line with CLIC.
Verification of RISCV ISA : C and Assembly level test cases for the functional verification of R-type , I-type , S-type , B-type and J type instruction.
UVM based Verification of TAP controller (JTAG - standalone) , Synchronous FIFO module, APB Master- Slave

Test PatternGate Level SimulationAutomatic Test Pattern Generation (ATPG)Universal Verification Methodology (UVM)Computer ArchitectureSystemVerilog+4

Senior Engineer , System Design Engineering

Jul 2018 – Jan 2019 · 6 mos · Bangalore , India

System Level Design of SD/uSD cards for better quality, performance and reliability.
Failure analysis at NAND and SD interface through trace analysis (Frontend and backend trace).
Familiarity to NAND/Flash Interface (ONFI protocol) for resolving NAND command sequence related issues and performance optimization .
Automated NAND sequence validation via Python scripting.

Sandisk, a western digital brand

System Design Engineer

Jul 2016 – Jul 2018 · 2 yrs · Bengaluru, Karnataka, India

Firmware Development for SD/uSD : Both designed & coded Firmware architecture scheme for improving write performance in SD/uSD cards.
Performance improvement using trackers to identify delays due to irregularities in firmware code (Dead code analysis).
Python based test scripts to identify corner case write patterns and their handling in firmware to bridge the gap between Low level memory level understanding and related abstract write/read schemes.

Society of robotics, dtu

Advisor, Training and Placement

Aug 2015 – Jun 2016 · 10 mos · Greater Delhi Area

Guiding the students regarding Internship and Placements procedures and hiring tests.

Sandisk

System Design Engineer

Jun 2015 – Jul 2015 · 1 mo · Greater Bengaluru Area

Summer Intern
SanDisk is a multinational corporation that specialises in delivering data storage solutions and technology.
I studied the design and working principle of NAND Flash memory, SD and uSD cards and worked in CE RPG SD uSD Team.
Projects completed:
1. CNE characterisation for SD/uSD systems
2. Python based parser for Low level system validation automation
3. Bad Block Injection Automation
4. Raw Performance Trimming Automation
5. SD/uSD Video Recording Replication
6. Peak Power Simulator Tool
The tools were simulated using Python 2.4