Apr 2021 – Sep 2022 · 1 yr 5 mos

• Developed and implemented a low power implementation methodology in the team, which improved dynamic power by 15%+ across designs. These findings were also shared with the entire physical implementation community at Arm
• Work closely with the RTL teams to provide feedback and identify opportunities for area and power improvements
• Collaborate with IP teams for physical IP definition for low power/area instances tuned for GPUs and little.CPU Arm processors
• In collaboration with logic IP teams, provided implementation feedback for development of best-in-class GF 28nm libraries
• Co-authored/presented 2 out of 3 papers selected from the entire PDG division in the Arm Regional Engineering conference,2021
• Mentor for several graduate engineers and interns in the team
• Administrative responsibilities include technical guidance, milestone scheduling within project, design reviews and hiring new talent for diversification and growth of the team.
• Additional responsibilities of PPA pre-sales and support for variety of ARM CPU IPs across Cortex-A/R/M class of cores & GPUs for client, infra and automotive segments

Apr 2019 – Apr 2021 · 2 yrs

• Synthesis-to-STA implementations on cutting edge technology nodes like 7nm,5nm
• Development of Cortex-A510 POP IP on advance FinFET nodes.
• Defined PPA targets, specifications & roadmaps for key POP engagements
• Technically lead POP projects to closure with successful execution throughout their lifecycle
• Head start into understanding characterisation flows for standard cells and memories to explore avenues for IP analysis and feedback
• Successfully delivered a memory re-characterisation project on 12nm with 100% silicon yield

Jan 2017 – Mar 2019 · 2 yrs 2 mos

• Synthesis - to - STA closure of Arm CPUs & subsystems,
• Static Timing Analysis,
• Physical Verification & power/IR closure,
• Physical IP and Power-grid methodology tuning
• Implementations spanning multiple nodes - 28nm, 16nm, 14nm across multiple A-class Arm CPUs and subsystems – CA53, CA72, CA55, CA75, DynamIQ on multiple EDA flows
• Performed additional responsibilities towards customer-facing pre-sales, engineering and support areas for Arm POP products across multiple sites.

Jul 2015 – Dec 2016 · 1 yr 5 mos

• Performed development on dual EDA flows for exhaustive implementation solutions.
• Worked on developing an internal tool to automate floor-planning for Arm cores. Defined the methodology, user-inputs and compared results with industry standard EDA tools

Dec 2014 – Feb 2015 · 2 mos · Noida, Uttar Pradesh, India

• The aim of this project was to understand about Regression Management Suites and implement features to automate several tasks during simulation and emulation.
• The Regression management Suite used was VRUN manager and various features were implemented on it.

Jun 2014 – Jul 2014 · 1 mo

• 1. Sucessfully completed the RAM integration and verification for 64K Cortex A-53.
• 2. Setup the full synthesis to route flow for 10.5T based implementation.
• Value addition:
• 1. Head start on the 10.5T benchmarking for Cortex A-53.

Aug 2013 – Aug 2014 · 1 yr

Jul 2013 – Aug 2013 · 1 mo

• Studied the various type of transmitters used in industries. Also learned about PLC's and types of Control Valves used.

Aug 2012 – Aug 2013 · 1 yr · Delhi