Jay Maradia

Software Engineer

Ahmedabad, Gujarat, India7 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in UVM and SystemVerilog for verification.
  • Strong background in debugging and scripting.
  • B.Tech in Electronics and Communication Engineering.
Stackforce AI infers this person is a Verification Engineer in the IT and services industry.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)Systemverilog

Other Skills

DebuggingLinuxScripting

About

Experienced Engineer with a demonstrated history of working in the information technology and services industry. Skilled in Debugging, Linux, Scripting, Universal Verification Methodology (UVM), and SystemVerilog. Strong engineering professional with a B. Tech focused in Electronics and Communication Engineering from Ganpat University.

Experience

7 yrs 10 mos
Total Experience
7 yrs 10 mos
Average Tenure
7 yrs 10 mos
Current Experience

Einfochips (an arrow company)

2 roles

Senior Verification Engineer

Promoted

Jun 2021 – Present · 5 yrs

Universal Verification Methodology (UVM)SystemVerilogDebuggingScriptingLinux

ASIC Verification Engineer

Aug 2018 – Aug 2021 · 3 yrs

Universal Verification Methodology (UVM)SystemVerilogDebuggingScriptingLinux

Education

Ganpat University

B. Tech — Electronics and Communication Engineering

Jan 2015 – Jan 2018

Nirma University

Diploma — Electronics and Communication Engineering

Jan 2011 – Jan 2015

Stackforce found 100+ more professionals with Universal Verification Methodology (uvm) & Systemverilog

Explore similar profiles based on matching skills and experience

Ravindu Nimsara Perera

Ravindu Nimsara Perera

Senior Research And Development Engineer

at Syntax Genie (Pvt) Ltd

Colombo, Sri Lanka5 yrs 1 mo exp
Synopsys tools
CHANDAN JHA

CHANDAN JHA

Senior Hardware Engineer

at Qualcomm

Bengaluru, India5 yrs 9 mos exp
Physical DesignMicroarchitecture
Ajitesh Mishra

Ajitesh Mishra

Senior Engineer

at Sandisk

Bengaluru, India7 yrs exp
Application-Specific Integrated Circuits (ASIC)Hardware EngineeringFunctional VerificationSAPDevOps
Srinath Jeevakumar

Srinath Jeevakumar

Senior Architect

at NVIDIA

Bengaluru, India6 yrs 8 mos exp
Performance VerificationSilicon Bring-upPerformance Analysis
Shripad Deshpande

Shripad Deshpande

Head of R&D - Hardware Design and EDA

at Chipforge.ai

India27 yrs 2 mos exp
EDASoCVirtual PrototypingASIPRTL design
Ashutosh Rao

Ashutosh Rao

R&D Engineer

at Synopsys Inc

Bengaluru, India4 yrs 4 mos exp
Static Timing AnalysisCircuit DesignHardware Security
DG

Dinesh Kumar G V N

Senior Verification Engineer

at Qualcomm

Bengaluru, India6 yrs 11 mos exp
Unified Power Format (UPF)Universal Verification Methodology (UVM)
Shivaprasad Boddupally

Shivaprasad Boddupally

Analog Design Engineer

at Sophrosyne Semiconductor

Nalgonda, India4 yrs 4 mos exp
Analog Integrated Circuit DesignElectronic Circuit DesignSilicon Validation