Karthik Vedantham

Software Engineer

Bengaluru, Karnataka, India3 yrs 11 mos experience
Highly Stable

Key Highlights

  • Expert in ASIC Digital Design and Verification.
  • Strong foundation in SystemVerilog and UVM methodologies.
  • Proficient in multiple programming languages including Python and C.
Stackforce AI infers this person is a Digital Design Engineer specializing in ASIC development and verification.

Contact

LinkedIn

Skills

Core Skills

SystemverilogUniversal Verification Methodology (uvm)

Other Skills

USBDebuggingPerforceVerilogPython (Programming Language)CodeCoverageScriptingLinuxCMOSC (Programming Language)Xilinx VivadoIntel Quartus Prime

Experience

3 yrs 11 mos
Total Experience
3 yrs 11 mos
Average Tenure
3 yrs 11 mos
Current Experience

Synopsys inc

3 roles

ASIC Digital Design, Sr Engineer

Promoted

Jan 2024 – Present · 2 yrs 5 mos · Bengaluru, Karnataka, India

USBSystemVerilogUniversal Verification Methodology (UVM)DebuggingPerforceVerilog+8

ASIC Digital Design, Engineer

Jul 2022 – Jan 2024 · 1 yr 6 mos · Bengaluru, Karnataka, India

Intern (Techinal Engineering)

Feb 2022 – Jul 2022 · 5 mos · Bengaluru, Karnataka, India

Education

B. M. S. College of Engineering

BE - Bachelor of Engineering — Electronics and Communications Engineering

Jan 2018 – Jan 2022

FIITJEE

Jan 2016 – Jan 2018

Ravindra Bharti Public School

Jan 2016 – Present

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