Kishor Ingale — Software Engineer

● 18+ years of experience in ASIC/ FPGA flows and methodologies for design and verification at IP/subsystem/SoC level. ● RTL coding and verification with c/vhdl/verilog/systemverilog, mixed language simulation, assertion based verification. ● Expert in UVM/OVM/VMM methodologies. ● C/assembly based processor verification. ● Low power verification (dynamic/static) at IP/SoC level. Hands on experience with both CPF/UPF flows from writing power intent file at RTL level to verifying LP hardware inference from it in various stages of ASIC cycle. ● Expert in writing directed, constrained random test benches. Developing test/coverage plans, from specification. Experience of multiple IP/SoC verification, advanced debugging, expertise in VHDL, Verilog, SystemVerilog, C. ● Expert in Gate level simulation- from setup, debugging to closure. ● In depth knowledge of digital design and FPGA architecture. ● Good in Hardware debugging, proficient in handling digital storage oscilloscopes, logic analyzers, stroboscopes, parallel and serial port interfacing. ● Experience of major mainstream verification tools, such as VCS, NCSIM, Debussy/verdi, Questasim, Active-hdl, Modelsim, and many FPGA tools. ● Acquainted with signal integrity issues, PCB design, and PCB design tools such as OrCAD and PADS ● Have a proven track record of delivery in fast paced, mission-critical projects. Excellent in cross-site communication and coordination.

Stackforce AI infers this person is a seasoned ASIC/FPGA verification engineer with extensive experience in high-stakes technical environments.

Location: Bengaluru, Karnataka, India

Experience: 19 yrs 2 mos