Krushal Kaklotar

Software Engineer

Bengaluru, Karnataka, India7 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in DFT and ATPG methodologies.
Proficient in post-silicon validation techniques.
Strong background in logic synthesis and timing analysis.

Stackforce AI infers this person is a DFT Engineer specializing in semiconductor design and validation.

Contact

Skills

Core Skills

DftAtpg

Other Skills

Joint Test Action Group (JTAG)ATPG DRC analysisATPG pattern generationBlock level GLSNo-timing/Timing SimulationSimulation failure debugsMentor Graphics (Tessent)Synopsys (VCS, Verdi)Post-Silicon DebugSOC Single chain traceGate Level SimulationPost-Si ValidationAutomatic Test Pattern Generation (ATPG)ATPG SimulationsStatic Timing Analysis

About

Enthusiastic DFT Engineer

Experience

7 yrs 3 mos

Total Experience

3 yrs 7 mos

Average Tenure

4 yrs 9 mos

Current Experience

Amd

2 roles

Sr. Silicon Design Engineer

Jun 2024 – Present · 1 yr 11 mos

DFTJoint Test Action Group (JTAG)

Silicon Design Engineer 2

Aug 2021 – Jun 2024 · 2 yrs 10 mos

DFTJoint Test Action Group (JTAG)

L&t technology services limited

DFT Engineer

Feb 2019 – Aug 2021 · 2 yrs 6 mos · Bengaluru

ATPG DRC analysis and fixing.
ATPG pattern generation for Stuck-at & Transition fault models with EDT/EDT-
Bypass modes.
Block level GLS.
No-timing/Timing Simulation for min/max corners of Chain, Stuck-at and At-speed patterns.
Simulation failure debugs for Timing/No-timing.
Tools: Mentor Graphics (Tessent), Synopsys (VCS, Verdi)

ATPG DRC analysisATPG pattern generationBlock level GLSNo-timing/Timing SimulationSimulation failure debugsMentor Graphics (Tessent)+3

Sandeepani- school of embedded system design

DFT Trainee

Aug 2018 – Feb 2019 · 6 mos · Bengaluru, Karnataka, India

Trained in DFT (Design for Testability)
Trained in RTL Synthesis flow. FV-LEC (Formal Verification) Flow.
Have Good knowledge of MBIST, LBIST, JTAG (IEEE1149.1), IJTAG (IEEE P1687) and IEEE P1500.
Have excellent knowledge of Scan Compression, ATPG, GLS.
Worked on ATPG Pattern Generation (Tessent) and Pattern Simulations (VCS, Verdi)