Kunj Shah

Software Engineer

Bengaluru, Karnataka, India10 yrs 6 mos experience

Highly Stable

Key Highlights

7 years of experience in Pre-Si Cache Coherency verification.
Led verification for multiple Intel Icelake Server SOCs.
Published research on system config optimization.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in SoC design and verification methodologies.

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Skills

Core Skills

Config RandomizationTest PlanningSystem On A Chip (soc)Cache Coherency

Other Skills

VerilogSystemVerilogUVMLUA ScriptingUnit Test AutomationField-Programmable Gate Arrays (FPGA)Very-Large-Scale Integration (VLSI)System ArchitectureMeshcxlCadence VirtuosoMicrocontrollersEmbedded SystemsElectronicsMatlab

About

I have 7 years of Pre-Si Cache Coherency verification experience at SOC, Have spent these years writing test_bench, behavioral models from scratch to leading coherency domain verification for Intel Server SOCs. Part of coherency domain verification of four successfully taped-in (in market) Intel Icelake Server SOCs. I am very much interested in config randomization optimization at SOC, creating cross domain test plan for coherent fabric verification, finding new ways to solve cross die config/stimulus dependencies, writing SV stimulus to verify fabric and agents in UVM. I have published two research paper as author related to system config optimization in simulation test bench and four as co-author related to optimizations in test bench in DTTC Intel conference. Before joining Intel, I was Intern at Cisco where I developed Web authentication and authorization test framework. I have worked as Java developer before masters from BITS Pilani (Embedded systems), Since BTech days i have been interested in writing Arduino, Raspberry-Pi microcontroller code and always try to find ways to verify something holistically with less test cases. Always believe in learning new methodology and tools to achieve product verification faster with improved quality.

Experience

10 yrs 6 mos

Total Experience

4 yrs 4 mos

Average Tenure

1 yr 9 mos

Current Experience

Nvidia

Senior Verification Engineer

Aug 2024 – Present · 1 yr 9 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

2 roles

Fabric verification lead

May 2023 – Aug 2024 · 1 yr 3 mos · Bengaluru, Karnataka, India · On-site

Leading coherent fabric verification team responsible to sign-off MultiChipPackage simulation for next server SoC
Key member of Infra team to bringup testbench for two Xeon server SOCs.
Defined strategy for address map alignment of multiple dies in multi-chip package simulation and implemented it
Successfully taped-in rapid and forest line server SoC
Go to person for cross domain RTL debugs, any issues related to system config randomization and sequence coding.

Test PlanningConfig randomization

System-on-Chip Design Engineer

Jul 2017 – Apr 2023 · 5 yrs 9 mos · Bengaluru, Karnataka, India · On-site

During journey successfully taped-in (in business) two Icelake server SOCs and currently leading Coherency verification for latest Xeon Intel server SOC.
Contributed in test plan implementation of Coherency cross products with reset, power management, security features and developed content for it.
Part of coherent fabric Pre-Si verification at SOC for Intel Icelake server products, Have contributed to analyze spec, design test plan and efficiently execute it.
Developed test_bench, verification environment from scratch following UVM at SOC for two Server SOCs.
Came up with efficient config randomization methodology and implemented it for Intel server SOCs.
Contributed to Behavioural Model implementation of RTL blocks to verify individual domains/IPs quickly at SOC.
Developed System Verilog stimulus to verify Coherent Fabric, bridges to core,CXL,memory controller at SOC.
Written assertions, coverage and scripts to reduce manual effort in segregating assertions, coverage bins.

Config randomizationVerilogSystem on a Chip (SoC)

Cisco

Intern

Jan 2017 – Jun 2017 · 5 mos · Bengaluru, Karnataka, India

Worked as an Intern for Core Software Group, Cisco. Project details include, integration of Cisco proprietary Test framework with Code modules for Unit Test Automation which is beneficial for Developers to reduce development time by automating White box testing. Test cases are written in LUA Scripting from which C functions can be called via Foreign Function Interfacing. Implemented test cases for multiple dot1x MD5 and Webauth based Authentication sessions for Cisco Trust Sec product.

Infosys

2 roles

Senior System Engineer

Apr 2015 – Jul 2015 · 3 mos · Pune/Pimpri-Chinchwad Area

Along with core development and Unit test work, i was involved in discussions with client and business analysts for upcoming technical changes in Trade booking application.
Won Infosys Insta Award for outstanding performance.

System Engineer

Jun 2013 – Mar 2015 · 1 yr 9 mos · Pune/Pimpri-Chinchwad Area

Worked as a Java developer for one of the leading investment bank. The software involves Over The Counter trade booking. Technologies involved are JMS(Java Messaging Services),Core JAVA, Spring, Struts, jsp, JPA, SQL.
My work involved modification of business rules as and when required due to regulatory requirement. Add/remove fields in user interface (website) based on regulatory requirements. Accommodate new fields and apply business validation rules on new fields added by upstream.