M

Manish S

DevOps Engineer

Bengaluru, Karnataka, India15 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 14 years of experience in design verification.
  • Expertise in UVM and functional verification.
  • Proficient in automation using Perl.
Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in UVM and functional verification.

Contact

LinkedIn

Skills

Core Skills

UvmFunctional Verification

Other Skills

UVM RALSERDESAHBAPBMDIOPerlSystemverilogPCIeVerilogVLSISynopsys toolsPERL

About

DV engineer with 14 years of work experience on SV and UVM

Experience

15 yrs 10 mos
Total Experience
3 yrs 2 mos
Average Tenure
4 yrs 3 mos
Current Experience

Amd

SMTS

Feb 2022 – Present · 4 yrs 3 mos · Bengaluru, Karnataka, India

Qualcomm

Sr. Lead DV Engineer

Jul 2017 – Feb 2022 · 4 yrs 7 mos

Broadcom limited

Design Verification Engineer

Mar 2012 – Jul 2017 · 5 yrs 4 mos · Bengaluru Area, India

  • Verification of the register set using UVM RAL.
  • Coding testcases for verification of various features related to SERDES .
  • Coded UVM agents for bus protocols (AHB, APB and MDIO) from scratch
  • Worked on functional coverage coding and coverage closure .
  • Testplan for the register verification.
  • Automation for the generation of register model and regression using Perl.
  • Regression debug.
UVM RALSERDESAHBAPBMDIOPerl+2

Lsi corporation

Contractor

Dec 2010 – Mar 2012 · 1 yr 3 mos · Bengaluru Area, India

  • Regression running and debug for Systemverilog testcases.
  • Running sanity checks on the design before it goes for GDS.
  • Scripting for automation of result collection in PERL.
SystemverilogPERLFunctional Verification

Cognizant technology solutions

Programmer analyst

Jul 2010 – Dec 2010 · 5 mos · Bengaluru Area, India

Education

Birla Institute of Technology and Science, Pilani

Master of Technology (M.Tech.) — Microelectronics

Jan 2013 – Jan 2015

Amrita School of Engg

B.Tech — ECE

Jan 2006 – Jan 2010

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