Dec 2024 – Present · 1 yr 5 mos · Hybrid

• Owned front-end implementation and STA closure for High Speed Interface IP's driving execution from RTL to scan-inserted netlist, including synthesis, LEC, CLP, pre-layout STA, and signoff readiness.
• Mentored junior engineers on SDC authoring, STA debug, and synthesis QoR analysis, establishing consistent closure and constraint quality practices for various top tier customers.
• Authored and validated mode-aware, multi-corner SDC constraints for high-speed interfaces including
• USB 3.x / USB4 (5 / 10 / 20 / 40 Gbps) and PCIe Gen4 (16 GT/s), covering functional, scan, and low-power modes.
• Hands-on ownership of complex clocking and timing constraints, including integration support for subsystem and SOC vendors.
• Developed and verified UPF-based low-power intent, performing VCLP checks, power state validation, and timing analysis across multiple power domains and modes.
• Executed constraint verification and completeness checks using TCM, Galaxy Constraint Analyzer, and custom validation flows to catch tool-gap and corner-case violations.
• Performed DFT-aware timing and constraint signoff, including scan constraints, test clocks, DFT DRC checks, and resolving timing issues across functional and test configurations.
• Drove in-depth synthesis and PTPX analysis, optimizing area, power, and timing; identified RTL design fixes to reduce critical path depth, unnecessary toggling, and synthesis pessimism.
• Built custom Tcl/Python and AI-assisted automation to accelerate STA debug, constraint validation, synthesis analysis, and signoff convergence.
• Supported silicon bring-up and customer debug, tracing post-silicon issues back to RTL, constraints, and netlist behavior.

May 2023 – Dec 2024 · 1 yr 7 mos · Hybrid

• Worked on intricate details of VLSI design flows, focusing on making nichè optimizations that drive performance and efficiency. My work involves understanding the industry protocols and constraining the High Speed serdes IP's, including PCIe4, USB3.x, USB4/USB4v2, DP, DP_HDMI, and HDMI 2.1, which we implement to meet cutting-edge design requirements ensuring the PPA efficiency and STA closure across MCMM scenarios.
• Developed from scratch and rigorously validated full IP level constraints for ~10G HDPCS block. Utilised design knowledge, Constraints, Tools knowledge to meet all params (PPA) .

Jan 2023 – May 2023 · 4 mos · Hybrid

• During my internship, I gained a solid foundation in RTL design, Constraints Writing, Validation focusing on creating and enhancing robust frontend synthesis flows optimized for low power and area efficiency. I developed parsers to extract actionable insights from logs and reports, driving design improvements.
• Utilizing Synopsys tools like Design/Fusion Compiler, Formality, VCLP, TCM, GCA, ATPG,PrimeTime etc. I implemented key design changes, contributing to more efficient and reliable semiconductor designs.

May 2021 – Aug 2021 · 3 mos · Noida, Uttar Pradesh, India

• Pepcoding is an Ed-Tech dedicated to technical- upskilling and bridging industry-academia gap to enhance employability of technical graduates and working professionals.
• My role was of a Teaching Assistant at the institute, where my key responsibilities were to explain the Concepts of Data Structures and Algorithms, Code optimization, Error handling and Debug the codes written in Java.

Feb 2021 – Jun 2021 · 4 mos · New Delhi, Delhi, India

• Worked with Dean , Associate Dean and other alumni staff to assure coordination and development of total alumni relations program ; recommend long and short- range goals and overall direction of alumni programs.
• Performed necessary administrative functions such as record keeping , reports , correspondence, program budget oversight, as necessary ; maintained records and supervise book keeping , reconcile accounts , monitor investments , within alumni association.

Aug 2019 – Jan 2023 · 3 yrs 5 mos · New Delhi, Delhi, India · Hybrid

• Worked under the pressure and responsibility of arranging every detail involved in preparing for exhilarating and spectacular sports event , successfully organized 11+ events as of now.
• Coordinated with teams of varying sizes and directly led a team of 15+ Student Volunteers to guarantee that every aspect of the sporting event is under control.
• Planned carefully to keep venues operating efficiently and minimize wasted expenses..
• Provided technical support by making score keeping apps so that their occurs no ambiguity in the scoring procedures .