Pratyush Patel — Software Engineer
As a Design Verification Engineer at Google, I work on verifying complex SOC/IP/ASIC designs using UVM, SystemVerilog, and Python. I have experience in creating verification environments, test cases, assertions, and coverage to verify various blocks and protocols in SOC. I also work closely with the design team to debug and report bugs in the design, and to ensure verification plan completion on all desired metrics. I have a strong interest and knowledge in digital design concepts, ASIC verification flow, and test bench architecture. I have also worked on several projects in the field of robotics and automation, using different controllers, sensors, and programming languages. I am passionate about learning new technologies and skills, and contributing to the innovation and quality of the products and services I work on. The following is some of my skills and Specialties : Technical Skills : 👉 Languages: System Verilog, Verilog, C++, Python 👉 Verification Methodologies: UVM 👉 Protocols : AHB, APB, I3C, I2C, SPI 👉 EDA Tools: Cadence Simvision, SYNOPSYS VCS, DVE, Questa Sim Specialties: 👉 Good knowledge of fundamentals of Digital Design Concepts. 👉 Depth Understanding of the ASIC Verification Flow, Test Plan & Test bench architecture. 👉 TB Architecture and Test Plan Development 👉 Proficient in Verilog & SystemVerilog & Knowledge of UVM. 👉 Worked on Assertion development, Functional coverage & Created functional tests. 👉 Worked on code coverage analysis and coverage closure. 👉 Worked on end-to-end data path verification. 👉 Worked on IP-level verification. 👉 Worked on Chip level verification of sub-block. 👉 Hands-on experience in the verification of Protocols such as SPI, I2C, I3C, APB, and AHB. 👉 Worked closely with RTL designers to specify, develop and debug constrained-random and directed test cases toward coverage-driven verification closure.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and digital design.
Location: Bengaluru, Karnataka, India
Experience: 4 yrs 8 mos
Skills
- Universal Verification Methodology (uvm)
- Asic Verification
- Protocol Verification
- Functional Verification
- Verification Closure
- Debugging
- Robotics
- Pcb Design
Career Highlights
- Expert in ASIC verification with UVM and SystemVerilog.
- Led projects achieving significant defect reduction and quality improvement.
- Strong background in robotics and PCB design.
Work Experience
Design Verification Engineer (L4) (6 mos)
Design Verification Engineer (L3) (1 yr 9 mos)
eInfochips (An Arrow Company)
Design Verification Engineer (2 yrs 5 mos)
Penguin engineering
Intern (1 mo)
GTU Robotics Club
Core team member (2 yrs 2 mos)
Education
Bachelor of Engineering - BE at Vishwakarma Government Engineering College
