Prodip Kundu

Product Engineer

Bengaluru, Karnataka, India21 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 9 years of experience in ASIC & FPGA verification.
Expertise in PCI Express protocol and UVM methodologies.
Proven track record in EDA tool development and testbench creation.

Stackforce AI infers this person is a Semiconductor and EDA expert with extensive verification and tool development experience.

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Skills

Core Skills

Functional VerificationSoc/sub System Level VerificationFpga VerificationEda Tool DevelopmentTest Bench Development

Other Skills

PCI Express protocolSVUVMDebuggingGate Level SimulationFunctional SimulationVHDLVerilogTool DevelopmentXMLPerlSystem VerilogSVAPSLModelSim

About

Experience Summary - 9+ years industry experience in ASIC & FPGA verification & EDA tool development domain. - M.Tech. in Computer Science & Engineering. - Expertise in PCI Express protocol, System Verilog,SVA, UVM. - Experience in Testbench development using UVM,SV & handling VIPs (Verification IPs). - Knowledge of ARM architecture ,AMBA bus protocols: AHB, AXI. - Exposure to X-86 based processor architecture verification. - Hands on in C, C++, Perl, shell scripts, TCL, Version control. - Experience in Synthesis, Gate Level Simulation. Specialties: - SoC/Sub System level verification, Coverage closure, X86 micro-architecture, Assembly language , Logic Design, Gate Level Simulation, Verilog, System Verilog and verification methodologies like UVM , EDA Tool Development , C, C++, Perl , XML , Shell Scripting ,Debugging Tools ( Verdi, GDB) etc.

Experience

21 yrs 5 mos

Total Experience

4 yrs 1 mo

Average Tenure

11 yrs 2 mos

Current Experience

Arm

2 roles

Principal Verification Engineer

Promoted

Apr 2021 – Present · 5 yrs 1 mo

Staff Verification Engineer

Feb 2015 – Mar 2021 · 6 yrs 1 mo

Amd

SDE

Jul 2011 – Feb 2015 · 3 yrs 7 mos · Bangalore

Worked on verification of PCI Express protocol.
Testbench development using SV & UVM.
Worked on full Chip Verification team of next generation AMD SoCs – debugging functional anomalies of assembly language tests (based on X86 architecture).
Gate Level Simulation activities for AMD SoC.
Contribution in design verification infrastructure – debugging complex verification environment issues, developing tools to support complex compilation flow, handling various regression and testlist management tools, flow automation etc.

PCI Express protocolSVUVMDebuggingGate Level SimulationFunctional Verification+1

Microsemi corporation

Sr. Engineer - FPGA

Dec 2009 – Jul 2011 · 1 yr 7 mos · Greater Hyderabad Area

Worked on verification of Actel's(now Microsemi) FPGA product line and related tools and FPGA flows (Functional & Gate level Simulations, Synthesis , Designer Layout ,Timing Analysis, Programming file generation etc.) used by customers to design and program Actel FPGA devices.
Ownership of new features verification of SmartFusion (Intelligent Mixed-Signal FPGA).
Developed test designs in VHDL and Verilog, test benches, and test scripts.
Developed, maintained complex Regression infrastructure to automate test execution.
Was responsible for benchmarking of synthesis tools - performance analysis of Synplify pro with Precision RTL & Precision RTLPlus on top of Actel’s Designer Layout Tool.
Verification of new tool features like Auto connect – Automatic connections of single/multi processor based designs (ARM cores) & related peripherals (e.g. CoreAPBSram, CoreAHBSram, GPIO etc.), different Bus Interfaces ( Core AHBLite, CoreAPB3 etc.), Bridges ( AHBTOAPB3, CoreAHBTOAPB).

Functional SimulationGate Level SimulationVHDLVerilogFPGA VerificationFunctional Verification

Texas instruments

Team Member (Contractor)

Jul 2006 – Nov 2009 · 3 yrs 4 mos · Houston,Texas,USA

Worked on tool development that allows a chip or system designer to create the design specification once with different IPs and automatically generate all possible views– C/E Test case , RTF,HTML etc.
Worked on importing different Vendor Extension in Spirit Xml & Bitwise to ASHA conversion flow.
Managed ownership of ‘Automated Software & Hardware Abstraction’ (ASHA) flow for CSL (Chip Set Library) generation.
Worked on IP-Xact representation , DITA/DocBook for reusable documentation generation.
Creation of different ‘Perl Template Toolkit’ (PTT) based Testcase generators.

Tool DevelopmentXMLPerlEDA Tool Development

Interra systems

SMTS

May 2005 – Nov 2009 · 4 yrs 6 mos

Development of Test Bench and Test-Suite development using Verilog , System Verilog , SVA , PSL.
Checking of compatibility support of Test Suite using industry standard Simulators (Modelsim ,NCV ,VCS) & Validation of Synthesis Test Suite.

VerilogSystem VerilogSVAPSLTest Bench Development