Pushpanajali Pinnu

Software Engineer

Bengaluru, Karnataka, India19 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in chip/block implementation and timing closure.
Proficient in static and dynamic IR drop analysis.
Experienced in VLSI physical design methodologies.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and ASIC methodologies.

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Skills

Core Skills

Physical DesignTiming Closure

Other Skills

Static Timing AnalysisVLSIASICSoCPrimetimeTCLFloorplanningRTL designClock Tree SynthesisP&ROptimizationRouting

About

Experience in handling several aspects of chip level integration, floor-planning, design partitioning/releasing blocks for physical implementation and timing closure. Knowledge in power mesh design, Static & Dynamic IR drop analysis for single voltage and power gated designs Specialties: chip/block implementation and Timing closure

Experience

19 yrs 11 mos

Total Experience

5 yrs

Average Tenure

13 yrs 10 mos

Current Experience

Qualcomm

Lead Engineer, Sr

Jul 2012 – Present · 13 yrs 10 mos

Physical DesignTiming ClosureStatic Timing AnalysisVLSIASICSoC+5

Ibm

Sr Physical Design Engineer

Aug 2010 – Jul 2012 · 1 yr 11 mos

Amd

ASIC Design Engineer 2

Jun 2008 – Aug 2010 · 2 yrs 2 mos

Executed P&R for timing/area/power critical blocks from the stages floorplan to GDS
Owned timing closure for two clock domains at chip and block level.
Supported block level P&R at different stages, placement, CTS, optimization, routing and timing closure