Rajeev K — Director of Engineering

Over 20 Years Experience in VLSI Design, with specialization in Design For Test (DFT) and hands-on experience in Physical Design & STA. Taped out 20+ multi-million gate SoCs. Hands on experience on all aspects of Design for Test, from RTL to Post-Silicon. Worked across across different technology nodes from 165nm to 3nm, have expertise in Automotive SoC, Server SoC, Test-Chips and Mobile SoC. Experience in bringing-up different methodologies and flows. Specialties: Design For Test, Streaming Scan Network, Place and Route, Synthesis, Automatic Test Pattern Generation, Delay Fault Test. Small Delay Test, DFT Architecture, Reliability Test, Deterministic BIST, Compressed Scan techniques, Failure Analysis, Silicon Debug, Memory BIST, Static Timing Analysis.

Stackforce AI infers this person is a Semiconductor and Automotive expert with extensive DFT experience.

Location: Bengaluru, Karnataka, India

Experience: 23 yrs 8 mos