Rakesh Nyamagoud

Software Engineer

Bengaluru, Karnataka, India17 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in EDA tools for ASIC and FPGA design.
Strong background in formal verification and logic synthesis.
Proven leadership in managing complex software development projects.

Stackforce AI infers this person is a Senior Software Engineer specializing in Electronic Design Automation and mobile application development.

Contact

Skills

Core Skills

ManagementEdaLogic SynthesisSoftware Development

Other Skills

runtime optimizationplatform integrationRTL elaboratorVerilogVHDLdebuggingperformance improvementSoftware InfrastructureLimomobile application developmentLinux platformApplication-Specific Integrated Circuits (ASIC)RTL SynthesisPeople ManagementMobile Operating Systems

About

Experienced Senior Software Engineer with a demonstrated history of working in the field of Electronic Design Automation(EDA). Software development for ASIC & FPGA design flow EDA tools. Skilled in C, C++, ASIC & FPGA, Verilog, and VHDL. Strong engineering professional with a Bachelor of Engineering focused on Computer Science from Visveswaraiah Technological University.

Experience

17 yrs 8 mos

Total Experience

4 yrs 4 mos

Average Tenure

4 mos

Current Experience

Amd

Principal Software Engineer (PMTS)

Jan 2026 – Present · 4 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

Engineering Manager

Sep 2021 – Jan 2026 · 4 yrs 4 mos · Bangalore Urban, Karnataka, India · Hybrid

Engineering Manager and Senior Staff EDA Software Developer leading FPGA Quartus synthesis development, with a focus on logic synthesis, runtime optimization, logic optimization, memory inference, and platform integration. Responsible for supporting synthesis for next-generation Platform Designer (PD) and next-generation Quartus tools.

ManagementEDA

Synopsys

Senior Research And Development Engineer

May 2011 – Sep 2021 · 10 yrs 4 mos · Bangalore

Development and enhancement of formal verification tools, including Logical Equivalence Checking (LEC) and Formality ECO flows
Implementation of automated functional ECO (Engineering Change Order) solutions
Expertise in datapath equivalence checking algorithms
Strong working knowledge of Verilog and VHDL
Experience with RTL synthesis flows and optimization techniques
Familiarity with hardware design semantics and simulation behavior
Development of Verilog/VHDL parsers and compilers (readers)
Supporting and implementing new IEEE standard language features
Handling syntax, semantic analysis, and intermediate representations
Maintenance and enhancement of formal verification tools such as Synopsys Formality and ECO variants
Debugging and fixing tool issues (bug analysis, root cause, patching)
Improving performance, scalability, and correctness of verification engines

Logic SynthesisRTL elaborator

Samsung india software operation (siso)

Software Engineer

Sep 2009 – Apr 2011 · 1 yr 7 mos · Bengaluru, Karnataka, India

Design and development of a social networking project on mobile Linux platform.
Design and development of social networking sites as a native application in Samsung Linux mobile platform. Ex: Facebook, Twitter ...
Mobile application middleware software development for Linux platform.

Software InfrastructureLimoSoftware Development

Azingo inc.

Software Engineer

Jul 2008 – Aug 2009 · 1 yr 1 mo · Pune/Pimpri-Chinchwad Area

Design and development of Flash-Runtime framework on Open source Linux mobile platform.
Ported Adobe flashlite 3.1 Azingo mobile Linux platform.
Extended flashlite engine code to interact with native Linux platform.
Mobile application middleware development for Linux platform.