Ram Bahakar

Software Engineer

Bengaluru, Karnataka, India2 yrs 10 mos experience

Highly Stable

Key Highlights

Expert in DFT and Static Timing Analysis.
Strong foundation in VLSI System Design.
Hands-on experience with JTAG and ATPG methodologies.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in DFT methodologies.

Contact

Skills

Core Skills

DftStatic Timing Analysis

Other Skills

Joint Test Action Group (JTAG)VerilogAutomatic Test Pattern Generation (ATPG)Problem Solving

Experience

2 yrs 10 mos

Total Experience

2 yrs 10 mos

Average Tenure

2 yrs 10 mos

Current Experience

Mediatek

2 roles

Senior Engineer

Jul 2023 – Present · 2 yrs 10 mos

DFTStatic Timing AnalysisJoint Test Action Group (JTAG)VerilogAutomatic Test Pattern Generation (ATPG)

Intern

Jul 2022 – Jul 2023 · 1 yr

Education

National Institute of Technology Warangal

Master's degree — VLSI System Design(ECE)

Sep 2021 – Jul 2023

Government College of Engineering, Amravati.

Bachelor's degree — Electronics and Telecommunication Engineering

Aug 2016 – Aug 2020

Bharat Vidyalaya Akola

School

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