Ritesh Kumar Tiwari

Product Engineer

Allahabad, Uttar Pradesh, India4 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expertise in VLSI and ASIC design flow.
  • Proficient in multiple HDL and simulation tools.
  • Strong foundation in verification methodologies.
Stackforce AI infers this person is a VLSI Verification Engineer with expertise in ASIC design and verification methodologies.

Contact

Skills

Other Skills

Unified Power Format (UPF)PalladiumHardware EmulationSystemVerilogStatic Timing AnalysisAPBAMBAUniversal Verification Methodology (UVM)VerilogPython (Programming Language)

About

Looking to pursue a challenging career in the VLSI field and getting familiar with current technology, thus enhancing my knowledge and skills and complementing the company’s growth. Tools and Languages:  HDL: Verilog (Xilinx Vivado)  Simulation Tool: LTspice  Synthesis Tool: RTL Compiler  DRC/LVS Tool: Virtuoso (Cadence)  Programming Skills: C Technical Skills: •Familiar with the ASIC design flow from RTL to GDS-II, RTL Coding & Design, Static timing analysis(STA)

Experience

4 yrs
Total Experience
2 yrs
Average Tenure
3 yrs 1 mo
Current Experience

Cadence design systems

2 roles

Verification Engineer 2 ( Emulation Engineer )

Promoted

Jan 2024Present · 2 yrs 4 mos

Verification Engineer 1

Mar 2023Dec 2023 · 9 mos

Arm

Consultant (CPU Architecture Verification)

Mar 2022Feb 2023 · 11 mos · Bengaluru, Karnataka, India

Education

Indian Institute Of Information Technology Allahabad

M.Tech — Microelectronics

Jan 2019Jan 2021

University of Allahabad

Bachelor of Technology - BTech — Electronics and Communication Engineering

Jan 2015Jan 2019

Stackforce found 100+ more professionals with Unified Power Format (UPF) & Palladium

Explore similar profiles based on matching skills and experience