ROHIT RANJAN

Software Engineer

Ranchi, Jharkhand, India4 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expert in Physical Design with extensive block ownership.
  • Proficient in scripting for productivity and efficiency.
  • Designed an 8-bit RISC Pipeline processor in Verilog.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and scripting.

Contact

Skills

Core Skills

Physical DesignDftVerilog

Other Skills

Unified Power Format (UPF)TclTcl-TkInnovusStatic Timing AnalysisPrime timeDesign Rule Checking (DRC)Microsoft OfficeCustomer ServiceMicrosoft ExcelMicrosoft WordMicrosoft PowerPointLeadershipProject ManagementPublic Speaking

About

I have worked in Physical Design as a block owner in more then 8 blocks till now. I am good at scripting . I have written many scripts to make my work productive and efficient. Closed all block with good PPA. I have experience in N6, N4 AND N3 technology node. I know Innovus, tcl scripting, STA Analysis, Python scripting, Verilog. I have designed a 8 bit RISK Pipeline processor in verilog as my final year project in Masters.

Experience

4 yrs 10 mos
Total Experience
4 yrs 10 mos
Average Tenure
4 yrs 10 mos
Current Experience

Mediatek

2 roles

Senior Engineer (ISP Physical Design)

Promoted

Jul 2021Present · 4 yrs 10 mos

DFTUnified Power Format (UPF)Physical Design

Physical Design Engineer

Aug 2020Jun 2021 · 10 mos

DFTVerilogPhysical Design

Education

National Institute of Technology Karnataka

Master of Technology - MTech — VLSI DESIGN

Jan 2019Jan 2021

RCC INSTITUTE OF INFORMATION TECHNOLOGY 117

B.Tech — Electronics and Communications Engineering

Jan 2013Jan 2017

RCC Institute ofInformationTechnology

B. Tech — Electronics andCommunicationEngineering

Jan 2013Jan 2017

TENDER HEART SENIOR SECONDARY SCHOOL

12th — SCIENCE

Jan 2011Jan 2013

Tender Heart Senior Secondary School 10+2

High School — science

Jan 2011Jan 2013

Saraswati Vidya Mandir GUMLA

10th — ALL

Jan 2006Mar 2011

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