Roshan Bondse

Software Engineer

Bengaluru, Karnataka, India15 yrs 9 mos experience

Highly Stable

Key Highlights

13+ years in ASIC Physical Design.
Expert in Static Timing Analysis and Power Optimization.
Proven track record in training and mentoring new recruits.

Stackforce AI infers this person is a Semiconductor expert with a focus on Physical Design and ASIC methodologies.

Contact

Skills

Core Skills

Physical DesignElectronics DesignSynthesisTiming AnalysisTiming OptimizationEco ManagementTiming Closure

Other Skills

FoundriesRTL DesignECO FlowsRouting OptimizationTCLTapeoutStandard CellSystem on a Chip (SoC)MethodologyComputer-Aided Design (CAD)CAD ToolsVerilogEmbedded SystemsCModelSim

About

13+ years of experience in ASIC Physical Design. Tools, Flows and Methodology owner for leading projects. Conversant with Static Timing Analysis, Power optimization, Placement and Routing Construction flow deployment for multiple tech nodes for early TR/Production Novel flow development for Power optimization/Metal ECOs/Last mile closure Path Finding for PPA,TAT and Efficiency improvement Synthesis to GDS-II delivery of critical blocks on 14nm-3nm with Synopsys Tools Training new recruits for Synthesis, PnR and ECO flows Well organized with exceptional communication and people management skills.

Experience

15 yrs 9 mos

Total Experience

4 yrs 7 mos

Average Tenure

1 yr 11 mos

Current Experience

Nvidia

ASIC Physical Design Engineer - CAD/Methodology

Jun 2024 – Present · 1 yr 11 mos · Bangalore Urban, Karnataka, India · Hybrid

Sifive

Senior Staff Engineer

May 2023 – May 2024 · 1 yr · Bangalore Urban, Karnataka, India · Hybrid

Intel corporation

2 roles

Physical Design Engineer

Sep 2020 – May 2023 · 2 yrs 8 mos

Electronics DesignFoundriesPhysical Design

Graphics Hardware Engineer

Jul 2011 – Nov 2021 · 10 yrs 4 mos

Responsible for early identification and resolution of RTL issues for seamless synthesis execution.
Responsible for timing database creation and maintenance used to generate timing constraints for synthesis and P&R.
Development of RLS flows for timing and routing optimization.
Development of ECO flows to minimize database perturbation in post LV domain which resulted into faster ECO to tape-in cycle.
Successfully converged timing and routing of two blocks with 1.4M gate-count for 5 successive tape-ins.
Have good understanding of DC and ICC tools as primarily involved in flow development and block convergence.

Qualcomm india pvt.ltd, hyderabad

Interim Intern

Jul 2008 – Jun 2009 · 11 mos

Worked on the Vocoder front end development for Qualcomm Mobile Station Modem and the Incremental Build of the Vocoders and BIOS.
Worked on the Qualcomm Test Framework Development.

Hindustan aeronautics ltd., nasik

Summer Trainee

May 2006 – Jul 2006 · 2 mos

Extensive study of the GPS and other positioning systems like Galileo (global navigation satellite system) ,GLONASS.
Study of the Lean Management System.