Ruta Kothari — Operations Associate

I’m a Master’s student in Computer Engineering at Arizona State University (graduating May 2026), specializing in VLSI, digital design, and computer architecture. I have hands-on experience with complete ASIC flows using Cadence Innovus and Virtuoso, and my work spans the full RTL-to-GDSII design flow - including logic synthesis, place-and-route, timing closure, and physical verification on advanced 7 nm design nodes. I’ve designed and optimized arithmetic units, logic paths, and hardware accelerators, focusing on achieving efficient power, performance, and area trade-offs. I’m currently seeking Spring 2026 co-op and full-time opportunities in physical design, digital design, and computer architecture.

Stackforce AI infers this person is a VLSI and digital design specialist with a focus on ASIC development.

Location: San Francisco, California, United States

Experience: 1 yr