Saket Thool

CEO

Bengaluru, Karnataka, India11 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in low-power Formal Equivalence Verification.
Proven track record in automation and scripting.
Strong background in VLSI and semiconductor projects.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in automation and low-power design.

Contact

Skills

Core Skills

Formal VerificationLow-power DesignAutomationFunctional Verification

Other Skills

Cascading Style Sheets (CSS)Application-Specific Integrated Circuits (ASIC)SystemVerilogConformal LECShell ScriptingLECDigital DesignsCLPCommunicationProblem SolvingQuality AuditingExploration and Production (E&P)Molecular MarkersPre-Owned VehiclesVerification and Validation (V&V)

About

*5+ Years experience in low-power Formal Equivalence Verification (FEV) using Conformal and Formality TFM. Skills acquired: LEC verification, Debugging, scripting, automation, Linux, TCL, Perl, python. *MTech in Communication System Engineering from VNIT Nagpur. * Worked as a Research Associate to fabricate SOC for a "low-power wireless sensor node " under the SMDP-C2SD Project Sponsored by MeitY at VLSI and Nanotechnology, VNIT Nagpur. * Worked as a Product Development Engineer at Electus Technologies Pvt. Ltd mainly worked on the development of industrial projects and instruments along with providing training to Engineering undergraduates on Embedded systems and electronics.

Experience

11 yrs 4 mos

Total Experience

2 yrs 11 mos

Average Tenure

5 yrs 8 mos

Current Experience

Intel corporation

3 roles

Technical Lead FEV

Promoted

Apr 2024 – Present · 2 yrs 1 mo

Cascading Style Sheets (CSS)Application-Specific Integrated Circuits (ASIC)Formal VerificationLow-power Design

System-on-Chip Design Engineer

Sep 2020 – May 2024 · 3 yrs 8 mos

SystemVerilogConformal LECShell ScriptingLECDigital DesignsCLP+2

Graduate Technical Intern

Jun 2019 – Sep 2020 · 1 yr 3 mos

SystemVerilogConformal LECLECCLPFormal VerificationLow-power Design

Intel india technology pvt. ltd.

System-on-Chip Design Engineer

Sep 2020 – Present · 5 yrs 8 mos

Dynamic Functional Verification Leader and Automation Expert serving as core signoff team member at Intel, driving TFM methodology development and cross-project verification excellence. Recognized for architecting comprehensive automation frameworks, sophisticated audit dashboards, and innovative VLSI solutions that streamline signoff flows while maintaining the highest quality standards. Proven ability to translate complex technical challenges into scalable, automated solutions that enhance organizational efficiency and verification closure across Intel's critical silicon programs.

AutomationFunctional Verification

Intel technology india pvt. ltd.

Graduate Technical Intern

Jun 2019 – Sep 2020 · 1 yr 3 mos

Responsible for low power Formal Equivalence Verification of partition level and full chip level runs till route stage. Developed autorun script for block level runs to Debug & reduce TAT. Developed automated audit script for Quality signoff of project. ECO and VCLP Have hands on experience of.

Formal VerificationLow-power Design

Visvesvaraya national institute of technology

2 roles

MTech in Communication System Engineering

Jul 2018 – Sep 2020 · 2 yrs 2 mos · Greater Nagpur Area

Communication

Research Associate

Jun 2017 – Jul 2018 · 1 yr 1 mo · Greater Nagpur Area

Worked at Centre for VLSI and Nanotechnology Department under SMDP-C2SD project sponsored by Ministry of Electronics and Information Technology (MeitY).

Conformal LECCLP