Saksham Gupta

Software Engineer

New Delhi, Delhi, India6 yrs 5 mos experience
Most Likely To Switch

Key Highlights

  • Expert in Physical Design for AI/ML chipsets.
  • Proven track record in static timing closure.
  • Hands-on experience with industry-standard design tools.
Stackforce AI infers this person is a Physical Design Engineer specializing in AI/ML chipsets within the semiconductor industry.

Contact

Skills

Core Skills

Physical DesignTiming Closure

Other Skills

Static Timing AnalysisCongestion OptimizationPlace & RouteCadence InnovusSynopsys Fusion CompilerSynopsys PrimetimePower DistributionManagementEvent ManagementMemory TestSRAMEmbedded SystemsCadence VirtuosoPython (Programming Language)System on a Chip (SoC)

About

• Physical Design Engineer - NPU (AI/ML) chipsets for the Snapdragon Mobile Platform, compute and automotive chips. • Execute floorplan and place & route for high logic density, multi-power domain designs across advanced process nodes including N2 GAA, SF2 GAA, N3E and N4. • Successfully taped out multiple projects with focus on achieving static timing closure and congestion optimization for complex low-power SoC designs. • Extensive hands-on experience with industry-standard tools including Innovus, Fusion Compiler, and PrimeTime. • Good understanding of clock tree synthesis to minimize skew & insertion delay and implementing effective ECO techniques along with resolving noise and crosstalk issues. • Knowledge of signoff checks including Static Timing Analysis, Physical Verification, EMIR analysis, Formal Verification, and Conformal Low Power checks.

Experience

6 yrs 5 mos
Total Experience
1 yr 6 mos
Average Tenure
2 yrs 11 mos
Current Experience

Qualcomm

2 roles

Engineer

Promoted

Nov 2024Present · 1 yr 6 mos · Noida, Uttar Pradesh, India

  • Working on NPU (AI/ML) chipset for mobile and automobile chip in the Physical Design domain
Physical DesignTiming ClosureStatic Timing AnalysisCongestion OptimizationPlace & Route

Associate Engineer

Jun 2023Nov 2024 · 1 yr 5 mos · Noida, Uttar Pradesh, India

Cadence InnovusSynopsys Fusion CompilerSynopsys PrimetimePhysical Design

Indraprastha institute of information technology, delhi

7 roles

Teaching Assistant - Memory Design and Test (ECE-611)

Jan 2023May 2023 · 4 mos

Teaching Assistant - Digital VLSI Design (ECE-514)

Sep 2022Dec 2022 · 3 mos

Undergraduate Research Assistant

Aug 2022Jan 2023 · 5 mos

  • Neuromorphic Computing
  • Advisor: Dr. Sneh Saurabh

Teaching Assistant - Embedded Logic Design (ECE-270)

Aug 2022Dec 2022 · 4 mos

Undergraduate Research Assistant

Dec 2021May 2023 · 1 yr 5 mos

  • Safety and Security Implementation in Circuits based on In-Memory Computation
  • Advisor: Dr. Anuj Grover

Teaching Assistant - Embedded Logic Design (ECE-270)

Sep 2021Jan 2022 · 4 mos

Undergraduate Research Assistant

Dec 2020Jul 2021 · 7 mos · Delhi, India

  • Implementation of wireless PHY on RFSoC
  • Advisor : Dr. Sumit J. Darak

Qualcomm

Interim Engineering Intern

May 2022Sep 2022 · 4 mos · Noida, Uttar Pradesh, India

  • Worked with the Modem Physical Design Team

Ieee iiit-delhi student branch

General Secretary

Sep 2019Mar 2021 · 1 yr 6 mos · Delhi, India

Education

Indraprastha Institute of Information Technology, Delhi

Bachelor of Technology - BTech

Jan 2019Jan 2023

Amity International School

High School Diploma — Science

Apr 2017Apr 2019

Amity International School, Noida

Apr 2010Apr 2017

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