Shashank Ukey — Software Engineer
Experienced Design Verification Engineer and Validation with a demonstrated history of working in the semiconductors industry. Skilled in Perl, Universal Verification Methodology (UVM), SystemVerilog. Strong and Verilog engineering professional with a Traning for Verification focused in VLSI-RN from Maven Silicon.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in VLSI design and verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 11 mos
Skills
- Universal Verification Methodology (uvm)
- Dfx
Career Highlights
- Experienced in Design Verification within the semiconductor industry.
- Proficient in Universal Verification Methodology and Perl.
- Strong educational background in VLSI and Electronics.
Work Experience
AMD
Sr. Silicon Design Engineer (3 yrs 9 mos)
L&T Technology Services Limited
Design Verification Engineer (2 yrs 8 mos)
Graphene Semiconductor Services Pvt Ltd.
Design Verification Engineer (1 yr 11 mos)
Maven Silicon
Trainee (7 mos)
Education
Master of Technology (MTech) at Yeshwantrao Chavan College of Engineering - YCCE
Traning for Verification at Maven Silicon
Bachelor of Engineering (BE) at Shri Gulabrao Deokar College of Engg Jalgaon
