Sruthy Jayakumar — Software Engineer
Working on static timing analysis, and parasetic extraction for ASIC signoff. Experienced in power grid analysis and power-grid fix using IR-aware PnR. - Actively driving deployment and qualification of "Tempus timing signoff" - Experience in Hier-STA, SI analysis, constraints debugging - Handled power grid analysis and fixing using "Innovus" - Worked in "Quantus" parasitic extraction, and correlation - Experience in PPA improvement experiments for sub-partition level designs - Developed and handled tcl based flows for automation of RC extraction, power-grid analysis, and fixing
Stackforce AI infers this person is a specialist in ASIC design and verification within the semiconductor industry.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 9 mos
Skills
- Cadence Tempus
- Power Grid Analysis
- Cadence Innovus
- Cadence Voltus
Career Highlights
- Expert in ASIC signoff with Tempus and Innovus.
- Proficient in power grid analysis and automation.
- Strong background in parasitic extraction and timing analysis.
Work Experience
Qualcomm
Senior Lead Engineer (1 yr 11 mos)
Cadence Design Systems
Lead Solutions Engineer (3 yrs)
Senior solution engineer (1 yr 10 mos)
Education
Master of Science - MS at Indian Institute of Technology, Madras
Bachelor of Technology - BTech at NSS College of Engineering, Palakkad
