Mar 2025 – Present · 1 yr 3 mos · Bengaluru, Karnataka, India

• Managing team of DFT scan insertion, DFT libs, Array DFT, ATPG

Mar 2021 – Mar 2025 · 4 yrs · Bengaluru, Karnataka, India

Jul 2016 – Feb 2020 · 3 yrs 7 mos

• Worked on :
• TestPlan creation & competition for Scan new feature of testing chip through PCIE. Leading a team of 8 member.
• Gate level Simulation debug methodology : working on debug of atpg vector comparison between vcs vs tetramax.
• System level ATPG vector testing via PCIE link : (RTL, Gate level, Intest and Extest pattern verification)
• Extest ATPG pattern conversion from STIL to system level format.
• DFTMAX ultra compression architecture understanding and pattern generation
• Leading ATPG DFT effort for System level Testing for GPU chips
• DFT LBIST Bring up done of LBIST pattern on system board
• LBIST testing for automotive chips - verification
• Translating STIL patterns from tetramax into specific format for automotive chips
• In system verification at full chip level for lbist patterns

Jun 2011 – Jul 2016 · 5 yrs 1 mo

• Worked on :
• In system testing/Verification of LBIST IP in verilog/system verilog
• xLBIST pattern verification
• Coverage and analysis of atpg patterns for SoC
• Developed verification setup for verifying all the scan modes by Tetramax & VCS simulation
• Synopsys new scan compression 1500 design - clock design to support all modes of scan.
• Synthesis of DFT clock design using design compiler - synopsys tool.
• Fast scan mode for part of GPU chips - Tetramax and vcs simulation
• ATPG Pattern generation and verification in FTM mode for GPU chips
• Scan Insertion for mobile SoC of 16nm
• Tetramax and coverage
• IEEE 1500 Jtag
• Mbist instertion - BIST logic generation
• Scan debug - verification
• Jtag and DFT clock verification
• ATPG and coverage analysis,
• Tcl, Perl scripting.
• Tools learn - Tetramax, VCS compiler, Verdi, DC compiler, Primtime timing tool,