Vaishnavi Jaiswal — Software Engineer
RTL Design Engineer with 4 years of experience in ASIC Design, SoC Design, Microarchitecture analysis and design of blocks. Proven Hands-on experience in RTL Coding and Validation using Verilog for block level implementations. Demonstrated expertise in Lint, CDC/RDC,LEC checks to ensure delivery of high quality RTL. Proven ability to seamlessly collaborate with cross functional teams to successfully resolve design challenges and achieve project objectives.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and SoC development.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 9 mos
Skills
- Microarchitecture
- Rtl Design
Career Highlights
- 4 years of experience in ASIC and SoC design.
- Expertise in RTL coding and validation using Verilog.
- Proven ability to collaborate with cross-functional teams.
Work Experience
Analog Devices
Senior Design Engineer (2 yrs 10 mos)
Intel Corporation
RTL Design Engineer (4 yrs 2 mos)
Indian Institute of Technology, Kharagpur
Teaching Assistant (9 mos)
Education
Master of Technology - MTech at Indian Institute of Technology, Kharagpur
Bachelor of Engineering at Institute of Engineering and Technology, DAVV,Indore
