Apr 2016 – Oct 2016 · 6 mos · Bangalore

• Setting up "DFT Center Of Excellence" to provide a real “consultant” experience to VLSI Service industry with technical expertise & complete ownership.
• ....sometimes just "vision" is not enough !! A great learning !!

Jul 2013 – Feb 2016 · 2 yrs 7 mos · Bangalore

Dec 2011 – Jun 2013 · 1 yr 6 mos · Bangalore

• Setting up "DFT Center of Excellence" to deliver state of the art DFT solutions for worldwide PMC products.

Jun 2009 – Nov 2011 · 2 yrs 5 mos

Feb 2006 – Nov 2011 · 5 yrs 9 mos

Dec 2004 – Feb 2006 · 1 yr 2 mos

• Worked on Baseband product (Technology node 65nm) in Wireless Division.
• Learned complete physical design (placement/clock tree buildup/ power routing etc) flow using Magma tools on ARM based design in 65nm technology node..
• Successfully completed 3-Days Physical Design Verification (Using Caliber) training delivered by Mentor
• S-GOLD3 based Baseband SOC : combines advanced EDGE modem technology with the latest multimedia functions.
• DFT specification creation
• Implementing DFT techniques SCAN, MBIST, JTAG, PLL Based At-Speed testing.
• DFT pattern generation & GLS
• Static Timing analysis using PrimeTime in SCAN , MBIST & JTAG mode.

Feb 2002 – Nov 2004 · 2 yrs 9 mos

• Worked on 3 Different Architectures (Technology node 90nm) in Wireless Domain.
• Managed a small team of contractors for execution.
• Delivered DFT training to other functional teams for better handshake of data & information.
• OMAP based Digital Baseband : a dual core processor that combines a TMS320c55x DSP core and TI-enhanced ARM925 processor. It is optimized for 2.5G and 3G wireless handsets and various multimedia applications.
• DFT Architecture changes & DFT Guide creation
• Test Block owner which involves RTL changes, synthesis & formal verification.
• MBIST generation, integration & verification.
• Scan insertion which involves defining scan insertion architecture, creating scan insertion scripts & performing scan insertion
• Test Coverage Analysis
• Timing simulation of ATPG patterns (TDLs) & pattern handoff to Test Engineering team
• DSP SubSystem : Based on DSP Core with some peripheral interfaces
• DFT Architecture changes & DFT Guide creation
• Closely worked with RTL designer to fix DFT DRC violations for test coverage improvement of IPs, which helped in increase of SOC Test Coverage.
• Scan insertion, ATPG pattern generation & gate level simulation.
• Deployed LED (Load Execute Dump) methodology for at-speed functional pattern generation.
• DRP : RF transceiver subchip bassed on the Digital Radio Processor (DRP) architecture.
• DFT specification creation as per tester and product engineering requirements.
• EDT Implementation & Scan insertion
• ATPG pattern generation , GLS & simulation environment creation using perl script
• Test Chip debug on VLCT tester based on same architecture

Jun 2000 – Feb 2002 · 1 yr 8 mos

• Lead the team of 3-4 members.
• Weekly customer interaction for project status update.
• Was responsible for Implementing different DFT features (scan insertion, test point insertion, boundary scan) in the customer designs (netlist).
• Worked on fixing DFT DRC violations during scan insertion, functional & ATPG pattern simulation with timing, JTAG implementation (Using BSDArchitect) & verification, pattern conversion (VCD to APF) and final pattern handoff to Product Engineering team.