Vipul Bondre

Software Engineer

Noida, Uttar Pradesh, India4 yrs 3 mos experience

Key Highlights

  • Expert in EDA and high-performance computing.
  • Achieved significant thermal hotspot reduction in semiconductor design.
  • Developed tools for scalable and efficient chip design.
Stackforce AI infers this person is a Semiconductor EDA specialist with a focus on high-performance computing.

Contact

Skills

Core Skills

Eda & Circuit VerificationHigh-performance Computing

Other Skills

AIGsAlgorithm OptimizationAlgorithmsAssembly LanguageBDDsBlockchainC (Programming Language)C++CSSCircuit Equivalence CheckingCustomer ServiceDRC ComplianceData MiningData StructuresGit

About

Hi, I'm a Senior R&D Engineer specializing in EDA (Electronic Design Automation) and high-performance computing. I focus on optimizing physical signoff fill, circuit equivalence checking, and scalable software solutions for semiconductor design. With expertise in C++, multithreading, and algorithm optimization, I develop tools that enhance performance, scalability, and efficiency in chip design. 🔗 What I Do • Develop and optimize fill runsets to mitigate thermal issues in sub-2nm technology nodes. • Enhance physical signoff methodologies while ensuring DRC compliance and manufacturability. • Implement high-performance EDA tools for circuit equivalence checking (CEC), integrating AIGs, BDDs, and multithreading for speedups. 🌟 Professional Experience SYNOPSYS INC. | Senior R&D Engineer 📍 Jan 2024 – Present | Noida • Developed and managed fill runsets in the Physical Signoff Fill team, achieving up to 30% thermal hotspot reduction in advanced nodes (<2nm). • Improved functionality, performance, and scalability of signoff fill solutions while ensuring compliance with manufacturing constraints and DRC rules. X-EPIC CORP. LTD. | R&D Engineer II 📍 July 2022 – Jan 2024 | Noida • Developed a hybrid Circuit Equivalence Checking (CEC) approach integrating AIGs and BDDs after an extensive literature survey. • Implemented and scaled a proof-of-concept, improving CEC efficiency for larger designs and achieving a 10x speedup through multithreading-based parallelization. • Designed and implemented 30+ commands for circuit query, circuit editing, and guidance functionalities in the CEC product development team. 🧠 Skills & Expertise • Programming: C++, Python, JavaScript • EDA & Circuit Verification: Signoff Fill, Circuit Equivalence Checking (CEC), AIGs, BDDs • High-Performance Computing: Multithreading, Algorithm Optimization, Parallel Processing • Tools & Frameworks: Shell Scripting, Linux, Vim, GDB 📫 Let's Connect! I’m always open to discussions on EDA, semiconductor design, and system optimization. Feel free to reach out!

Experience

4 yrs 3 mos
Total Experience
1 yr 1 mo
Average Tenure
11 mos
Current Experience

Cadence

Lead Software Engineer

Jul 2025Present · 11 mos · Noida, Uttar Pradesh, India

C++MultithreadingAlgorithm OptimizationSignoff FillDRC ComplianceEDA & Circuit Verification+1

Synopsys inc

Sr R&D Engineer

Feb 2024Jul 2025 · 1 yr 5 mos · Noida, Uttar Pradesh, India · Hybrid

AIGsBDDsMultithreadingCircuit Equivalence CheckingEDA & Circuit Verification

X-epic

2 roles

R&D Engineer II

Jul 2022Jan 2024 · 1 yr 6 mos

Intern

Jan 2022Jun 2022 · 5 mos

Microsoft & iit ropar

Project Assistant

Jan 2022Jun 2022 · 5 mos · Rupnagar, Punjab, India · On-site

  • For Master's Thesis Project, working on funded project by Microsoft in collaboration with IIT Ropar under Dr. Viswanath Gunturi

Indian institute of technology, ropar

Teaching Assistant

Sep 2021Jan 2022 · 4 mos · Rupnagar, Punjab, India

  • Teaching Assistant for the Data Structures course

Education

Indian Institute of Technology, Ropar

M.Tech — Computer Science

Aug 2020May 2022

Govt. College Of Engineering, Aurangabad

Bachelor of Engineering - BE — Information Technology

Jan 2014Jan 2018

Resonance Eduventures Limited

High School — Engineering Science

Aug 2012Apr 2014

M.J.P. Junior College, Gokunda

High School Diploma — Science

Jan 2012Jan 2014

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