Jan 2013 – Aug 2014 · 1 yr 7 mos · Bangalore

• People Management Responsibilities
• Goal Setting, Performance measurement, Performance Appraisals, Coaching
• Creating collaborative work environment
• Organizing & conducting knowledge share sessions within the India team
• Organizing KT sessions conducted by experts or technical leaders located in different time zone
• Plugging communication gaps and conflict resolution
• Managing employee motivation
• Learning and skill development plans for employees and follow-up
• Technical Leadership Responsibilities
• == Lead development of simulation model for a third party network search engine IC
• Short schedule (two weeks) while working on another ASIC verification project in parallel
• Team ramped-up extremely quickly on specifications by sharing of knowledge gained individually
• Organized sessions with team that would use the model for ramp-up and understanding requirements
• Coding of the system verilog model, integration, debug shared by the team
• The behavioural model reduced regression time by a factor of 6 and this delighted the team using it
• == Lead verification of two complex subsystems in GEN6 Fiber Channel Switch ASIC
• Verification plan & TB Architecture
• Resource allocation, WBS & delegation of work responsibilities
• Reviews, course correction guidance, problem solving
• Weekly progress status monitoring and reporting
• Encouraging improvement suggestions and capturing leassons learnt

Aug 2009 – May 2012 · 2 yrs 9 mos

• ASIC Development Projects
• 1) First Generation Protocols Handler ASIC
• Verification of MAC talking to traffic manager via proprietary Ethernet links
• Verification of loopback block handling span, ospan, rspan, sflow packets
• Verification of routing engine (L3 protocols)
• 2) First Generation Traffic Manager ASIC
• Verification of MAC talking to protocols lookup chip via 14G proprietary links
• Simulations to prove that traffic manager and protocols chip would be able to talk via their respective XFIPCS and SERDES provided by two different vendors.
• 3) Second Generation Traffic Manager ASIC
• Design and verification of receive queues (linked list block) responsible for ensuring store-n-forward of packets
• Led design of Ethernet MAC talking to protocols lookup chip via proprietary protocol (re-architected due to vendor change and feature additions)
• 4) First Generation 10G/40G/100G switch ASIC
• Led verification of front facing MAC supporting all speeds upto 100G. 100G support was being provided for the first time in the company's history.

May 2012 – Jan 2013 · 8 mos · Pune/Pimpri-Chinchwad Area

• Ownership of SLIMPro verification in STORM
• Cortex M3 with peripherals
• Crypto DMA
• PKA (Public Key Accelerator)
• TRNG (True Random Number Generator)
• I2C Master/Slave Controllers - Master to read boot code from external I2C EEPROM.
• On chip Boot ROM, IRAM, DRAM
• AXI Application Interface to STORM IO Fabric via AHB-to-AXI bridge
• Controls power-up and boot including secure boot
• Symmetric secure boot with AES-GCM.
• Asymmetric secure boot using RSA algorithm
• Secure keys read from on-chip EFUSE

Feb 2008 – Jul 2009 · 1 yr 5 mos

• Worked on Thunderbird ASIC
• Verification of TMM

Jun 2004 – Jan 2008 · 3 yrs 7 mos

• Worked on Ethernet MAC IP products
• DMA design
• CRV Verification

Aug 2003 – May 2004 · 9 mos

• Worked on Verification of SoC IP
• Use of HVL (Specman e)

Jul 2001 – Jul 2003 · 2 yrs

• Worked on USB 2.0 & USB 1.1
• Participated in EHCI IP FPGA bring-up
• Worked on OHCI IP re-engineering