Yajur Pandit — Software Engineer

~14 Years Experience in bug hunting Able to motivate/lead/guide and drive multiple team members to achieve project goals and milestone. • Test Bench Architecture And Environment Development • Feature Extraction from RFC and Design Doc • Feature Plan, Test Plan, Checker Plan, Coverage Plan And Feature To Test Mapping • Firmware Development, Error Handling And Error Injection • Assertion And Cover Property Coding • Sanity And Regression Clean-Up • Function/Code Coverage Development And Closer • Architecture, Code Reviews • Basic Knowledge Of Automatic Formal Analysis Using Incisive Formal Verifier (IFV). • Implemented C++ Reference Model Have Ramp up multiple team members Have trained multiple interns from institutes like NITs for Oops, Systemverilog and UVM. Protocol : RoCE, IBT, RoCEv2, TCP, NVMeOf Over TCP, Ethernet, AMBA AXI4, AMBA AXI Steaming System Verilog, C, C++, UVM. Code coverage and Functional coverage analysis TLM1 & TLM2 Onsite experience : Hyderabad, India, Suwon, South Korea , California USA Hands on debugging Tools : VCS, QuestaSim and Cadence. Languages : System Verilog, Verilog, C, C++. Methodology : UVM.

Stackforce AI infers this person is a highly skilled ASIC Verification Engineer with extensive experience in functional verification and debugging.

Location: Bengaluru, Karnataka, India

Experience: 13 yrs 8 mos