Jan 2020 – Sep 2022 · 2 yrs 8 mos · Ahmedabad Area, India

• Experience in creation of test cases and debugging test and RTL issues.
• Good Knowledge in Perl, Shell and Makefile scripting.
• Good Knowledge in Assertion Based verification using SVA.
• Contributing in verification tasks such as Gate Level Simulations (GLS), Virtual Testing/PTE.
• Debugging regression failures both at IP/SOC level.
• Verification of Mixed - Signal or SoC automotive ASICs.
• Troubleshooting errors at any stage of the process.
• Capable of working both as an independent contributor and as a team member.

Jul 2019 – Jan 2020 · 6 mos · Ahmedabad Area, India

• Good Knowledge in ASIC verification flow.
• Worked on protocols (I2C, AXI and Router 1x3).
• Developed advanced verification environment and testbench components in System Verilog
• using UVM methodology.
• Execute the Verification test plan by developing checkers, stimulus and coverage using System
• Verilog and UVM.
• Create and maintain testbench at block level.
• Integration of VIP (Verification - IP).
• Generate tests, debug failures, evaluate coverage of design.

Jan 2019 – Jun 2019 · 5 mos · Ahmedabad Area, India

• The Training includes the understanding of ASIC
• verification modules along with the learning of verilog,
• system verilog and its features, UVM methodology.
• Worked on scripting language such as Perl and Shell.
• Worked on the Linux environment.