SWATHI M

Project Manager

Bengaluru, Karnataka, India8 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 5 years of experience in VLSI verification.
  • Proficient in System Verilog and UVM methodologies.
  • Strong background in digital communication and verification tools.
Stackforce AI infers this person is a VLSI verification engineer with expertise in digital communication and verification methodologies.

Contact

LinkedIn

Skills

Other Skills

Amba AHB-APBAssertion Based VerificationC (Programming Language)Code CoverageDigital CommunicationFunctional CourageLinxModel SimQuestasimSPI protocolStatic Timing AnalysisSystem verilogUniversal Verification Methodology (UVM)VHDLc

About

VLSI verification Engineer with 5 years of experience.

Experience

Synapse design inc.

2 roles

Senior Project Engineer

Promoted

Apr 2023 – Present · 2 yrs 11 mos

Design Verification Trainee Engineer

Apr 2018 – Apr 2023 · 5 yrs

Maven silicon

Design and Verification

Oct 2017 – Mar 2018 · 5 mos

Education

ACE Engineering college

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2012 – Jan 2016

ACE Engineering college

Intermediate — MPC

Jan 2010 – Jan 2012

Brilliant Grammer High School

Jan 2007 – Jan 2010

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