SIDDHARTH NAIR — Software Engineer
Proficient in SV and UVM based functional verification and basic experience in formal verification. Experienced in verifying consumer and automotive (ISO 26262 compliant) domain chips Have experience of leading a team of engineers for timely verification of 2 IP projects Have worked as part of team in functional verification of 4 SOCs adhering to strict guidelines. Experience of having worked independently for RAL based verification of processor subsystem block. Proficiency in async FIFO verification at IP and SOC level. Proficiency in verification of various serial communication peripheral such as I2C, I3C, SPI, SafeSpi Worked in IP/subsystem/SOC level verification environments. Have independently worked on block level using formal verification and achieved excellent results. Proficient in SVA. Proficient in PSL. Protocol familiarity- -------------------------------- PHY layer of Ethernet 400G,200G AMBA AHB 3 Lite AMBA APB I2C AMBA AXI UART SPI MIPI I3C SafeSpi V2.0 Tools- Proficient with VCS, NCSIM and Questasim. Proficient in Verdi and Simvision. Experienced with IMC planner.(Cadence) Proficient with VC_Formal. Have work experience in JasperGold Cadence. Comfortable on working with SVN and GIT version control systems. Misc. skills- Proficienct in C C++ Proficient in Python, Perl , Shell scripting languages Capable of working independently throughout the design verification cycle. Enthusiastic in facing challenges and working with team members to find appropriate and timely solution. Looking forward to work on challenging opportunities.
Stackforce AI infers this person is a VLSI Verification Engineer with expertise in automotive and consumer electronics.
Location: Ahmedabad, Gujarat, India
Experience: 7 yrs 9 mos
Career Highlights
- Led verification of automotive SOC adhering to ISO 26262 standards.
- Achieved 100% coverage on formal verification of Ethernet 400G.
- Designed custom UVM based memory manager for multi-master architecture.
Work Experience
eInfochips (An Arrow Company)
Senior engineer Lv2 (1 yr 7 mos)
Senior Engineer Lv1 (2 yrs 3 mos)
Application Specific Integrated Circuit Verification Engineer (2 yrs 9 mos)
Engineering Trainee (7 mos)
eiTRA - eInfochips Training & Research Academy Ltd
Verification Engineer (7 mos)
Education
BE - Bachelor of Engineering at Vishwakarma Government Engineering College