Ayush Hurkat — Software Engineer
Experienced Design Verification engineer with over 6 years of expertise in verifying complex IPs and subsystems. - Proficient in developing scalable verification environments using Systemverilog, UVM, and formal verification techniques including assertion-based checks and formal verification using JasperGold. - Hands-on experience in emulation workflows, including full system validation on Palladium, perspec driven coherency testing, and merging coverage data across simulation and emulation platforms. - Skilled in protocols like PCIe (Gen1-Gen5), AXI, AHB, APB, CAN. - Skilled in using industry standard tools such as Xcelium, Verisium debugger, Indago, VCS, Verdi, Vmanager for regression and vplan to drive high quality verification.
Stackforce AI infers this person is a Design Verification Engineer specializing in complex IP verification within the semiconductor industry.
Location: Jamnagar, Gujarat, India
Experience: 5 yrs 4 mos
Skills
- Design Verification
- Verification Environments
Career Highlights
- Over 6 years of experience in design verification.
- Expertise in SystemVerilog and UVM methodologies.
- Proficient in emulation workflows and full system validation.
Work Experience
Cadence Design Systems
Sr Solutions Engineer (3 yrs 3 mos)
eInfochips (An Arrow Company)
Design Verification Engineer (2 yrs 1 mo)
Project Trainee (1 yr)
Summer Intern (1 mo)
Education
BTech - Bachelor of Technology at Dharmsinh Desai University
Student at Shri P V Modi high school
