S

Sri Sruthi

Software Engineer

Bengaluru, Karnataka, India10 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expert in Design Verification for advanced SoC technologies.
  • Proficient in UVM and SystemVerilog methodologies.
  • Successful track record of multiple chip tapeouts.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in advanced SoC design methodologies.

Contact

LinkedIn

Skills

Core Skills

Design VerificationUvmSoc

Other Skills

Universal Verification Methodology (UVM)SystemVerilogVerilogLow power verificationBoot level simulationsGate level simulationsPower aware testingScriptingPower-aware verificationSynthesis to GDSII flowSemiconductorsIntegrated Circuits (IC)PerlMatlabArduino

About

. Working for the past 4 years in Qualcomm, Chennai. . Intern at Intel, Bangalore for 1 year. . Design verification Engineer with working experience in 7nm, 14nm, 28nm technology SoC chips. . Worked as Physical design engineer for a brief amount of time . Skilled in Universal Verification Methodology (UVM) and SystemVerilog, Verilog, Low power verification, RTL2GDSII flow . Strong engineering professional with a Master’s Degree focused in VLSI Design from Vellore Institute of Technology.

Experience

10 yrs 10 mos
Total Experience
2 yrs 2 mos
Average Tenure
2 yrs
Current Experience

Nvidia

Verification Engineer

May 2024 – Present · 2 yrs · Bengaluru, Karnataka, India · On-site

Qualcomm

3 roles

Senior Lead Engineer

Dec 2022 – May 2024 · 1 yr 5 mos

Senior Engineer

Promoted

Nov 2019 – Dec 2022 · 3 yrs 1 mo

  • Senior Design verification Engineer with working experience in 7nm, 14nm, 28nm technology SoC chips.
  • Skilled in Universal Verification Methodology (UVM) and SystemVerilog, Verilog, Low power verification, Boot level simulations, Gate level simulations and Power aware testing
  • Worked on 7 successful chips till tapeout stage
Universal Verification Methodology (UVM)SystemVerilogVerilogLow power verificationBoot level simulationsGate level simulations+3

Engineer

Jul 2017 – Oct 2019 · 2 yrs 3 mos

  • SOC level verification
  • IP level verification
  • Performance analysis on DV perspective
  • Power-aware verification
  • Synthesis to GDSII flow
  • Logical equivalence and functional equivalence checks,
  • Worked successfully on 5 tapeouts
  • Worked in Verification domain using UVM, System verilog and verilog .
  • Worked on 7nm, 14nm, 28nm related projects
  • Scripting proficiency in perl, tcl
UVMSystemVerilogVerilogScriptingPower-aware verificationSynthesis to GDSII flow+2

Intel corporation

Graduate Intern (physical design)

Aug 2016 – Jun 2017 · 10 mos · Bengaluru Area, India

  • . Modeling the timing libraries for the cells designed by the team.
  • . Performing ERC related checks on the mixed signal circuits in the MIG group.

Tcs

Assistant System Engineer

Aug 2014 – Jun 2015 · 10 mos · Hyderabad

Doordarshan

Trainee

Jul 2013 – Jul 2013 · 0 mo

Ignite

Volunteer

Sep 2012 – Feb 2013 · 5 mos

Education

Vellore Institute of Technology

Master’s Degree — VLSI Design

Jan 2015 – Jan 2017

V R Siddhartha Engineering college

Bachelor’s Degree — Electronics and Communication Engineering

Jan 2010 – Jan 2014

Narayana Junior college

High School

Jan 2008 – Jan 2010

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