Allola Nikhil Reddy

Associate Consultant

Hyderabad, Telangana, India6 yrs 5 mos experience

Highly Stable

Key Highlights

Expert in FPGA implementations for wireless applications.
Proven track record in DSP algorithm design and optimization.
Experienced in leading complex telecommunications projects.

Stackforce AI infers this person is a Telecommunications FPGA Design Expert with a focus on DSP algorithms.

Contact

Skills

Core Skills

Fpga DesignDsp Algorithm Design

Other Skills

3GPP5G5G New Radio (NR)AXIArithmeticCC++CI/CDContinuous Integration (CI)DSPDebuggingDigital Circuit DesignFPGAFPGA prototypingField-Programmable Gate Arrays (FPGA)

About

Experienced RTL design engineer specializing in FPGA implementations for wireless data-centric applications. 7 years working in fast-paced startups, turning abstract requirements into bit-streams that ship. Currently consulting and taking up independent projects. Key skills & hands-on experience - Expertise with Zynq Ultrascale+ and Intel Agilex; built baremetal and linux apps that span PS+PL. - DSP algorithm design and optimisation - FFT/IFFT, filters, Channel estimation and equalisation. - Implemented mod/demod chains and error correcting codes like LDPC, Polar and Reed-Solomon, delivering multi-gigabit throughput. - FPGA optimisation - expert in fixed point conversion, deep pipelining, and resource-latency tradeoffs for timing closure.

Experience

Redxp engineering

FPGA Consultant

Jan 2025 – Present · 1 yr 2 mos · Hyderabad, Telangana, India · Remote

Phytunes inc

Digital Systems Expert

Jan 2024 – Jan 2025 · 1 yr · Hyderabad, Telangana, India · Remote

Wisig networks

2 roles

Senior Engineer

Promoted

Aug 2020 – Jan 2024 · 3 yrs 5 mos

Led the design and integration of 2x2 gNB UL processing chain on a Xilinx FPGA, collaborating with the
rest of the L1 team to identify and fix bugs during integration.
Developed a 12 Gbps LDPC bit-processing IP core with HARQ support for an early stage 6G specification.
Designed, developed and integrated a FPGA vendor-agnostic PHY layer of the 2x2 UE stack for IAB-MT,
including creating L1 micro-architecture. Tested this design on Intel/Altera Agilex platform.
Created a System Verilog library containing scalable, efficient modules for fixed point arithmetic, AXI4
infrastructure, and essential dsp blocks including filters, correlators and cordic.
Developed a robust unit testing framework using Vunit and integrated it into the CI/CD build system.
Introduced an intuitive test case format, resulting in a significant acceleration of test case creation.
Recruited, onboarded, and trained new team members to ensure seamless integration into the project

FPGALDPCSystem VerilogCI/CDDSPFPGA Design+1

Research Engineer

Jun 2019 – Jul 2020 · 1 yr 1 mo

Designed and implemented an end-to-end 2x2 PUSCH processing channel capable of 1.2 Gbps PHY throughput using Vivado HLS.
Standardized the HLS coding style to optimize results and provided training to new team members.

5g iit-hyderabad

Project Associate

Jun 2018 – May 2019 · 11 mos · Hyderabad Area, India

Designed and implemented 5G NR PHY modules on Xilinx Zynq FPGAs using Vivado High level synthesis (HLS).
Worked on optimizing existing source codes related to PUSCH channel estimation and proposed new
ways to improve the throughput and latency using HLS.