R Pawan Kumar

Software Engineer

Bengaluru, Karnataka, India9 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 8 years of experience in semiconductor industry.
Expertise in advanced chip design processes.
Proficient in automation using scripting languages.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and VLSI technologies.

Contact

Skills

Core Skills

Asic DesignTiming ClosureSoc DesignPhysical DesignRadiation-hardened Design

Other Skills

10nm technology14nm technology28nm technology3nm technology5nm technology7nm technologyApplication-Specific Integrated Circuits (ASIC)CCTSCadence EncounterCadence VirtuosoClockClock Tree SynthesisCrosstalkDRC

About

Experience Over 8 years in the semiconductor industry, besides 1-year internship in a semiconductor laboratory, Dept. of Space, Govt. of India. Technical Expertise: • Hands-on experience with advanced TSMC and Samsung chip design processes, including 3nm, 4nm, 5nm, 7nm, 11nm, and 14nm technologies. • Strong knowledge of CMOS fundamentals and the ASIC design flow from RTL to GDSII, encompassing floorplanning, power planning, placement, CTS, and routing. • Proficient in planning and executing block-level PNR (Netlist to GDSII). • Expertise in timing closure at both block and SoC levels. • Handeled signingoff activities LEC, EMIR, PVR, QOR (STA) • Expertise in timing closure at both block and SoC levels • Skilled in managing low power and congested designs. Project Management: Successfully handled multiple projects throughout the PNR flow and tape-out activities. Tool Proficiency: Extensive experience with ICC2, Primetime, providing manual ECOs, ICV Workbench, Redhawk, and Tweaker tools. Automation Skills: Proficient in automation using Perl, TCL, and Python scripting.

Experience

Synopsys inc

2 roles

ASIC Physical Design Senior Staff Engineer

Promoted

Feb 2025 – Present · 1 yr 1 mo

SERDES-IP Design Experience:
Worked on multiple designs in 3nm, 5nm, and 7nm technologies using the latest TSMC processes.
PNR Flow Execution:
Executed complete PNR flow, including floorplanning, robust power planning, custom CTS plans for high-frequency hierarchies to minimize future ECO cycles while ensuring power optimized.
Timing Constraints and QoR:
Comprehended timing constraints from designers, achieving superior and faster Quality of Results (QoR). Internal Timing Path Analysis: Analyzed internal timing paths, addressed constraint issues, tuned clocks for skew balancing, generated ECOs for critical paths, and conducted
thorough analysis for min-max conflict paths across different corners. Performed crosstalk analysis, TDRC reviews, and resolved physical DRCs.
High-Frequency Clock Management:
Managed multiple high-frequency clocks within a single design, ensuring timing closure and power integrity

3nm technology5nm technology7nm technologyPNR flowpower planningCTS+6

ASIC Physical Design Staff Engineer

Apr 2021 – Present · 4 yrs 11 mos

Si2chip technologies pvt. ltd.

Design Engineer

Sep 2017 – Apr 2021 · 3 yrs 7 mos · Bengaluru, Karnataka, India

Worked on 5nm, 7nm, 10nm, 14nm and 28nm technologies.
Expertise at SoC level and Block level timing analysis, ECO generation and timing closure.
Expertise in handling congested designs timing closure and keeping power consumption in check.
Good knowledge on PNR flow, Timing concepts and Low power concepts.
Handling timing closure from synthesis to tapeout
Hands on experience in handling Innovus, ICC2, Primetime, Tempus and Tweaker tools
Good knowledge in Perl, TCL and shell scripting

5nm technology7nm technology10nm technology14nm technology28nm technologytiming analysis+6

Qualcomm

Physical Design Engineer

Sep 2017 – Apr 2021 · 3 yrs 7 mos · Bengaluru, Karnataka, India

Project Experience: Worked on multiple premium-tier Snapdragon 8 series and mid-tier 6 series mobile processors, including integrated 5G modems, DDR blocks, graphics blocks, and wireless technologies. Hands-on experience with the latest TSMC and Samsung chip design processes, including 5nm, 7nm, and 10nm technologies, with multiple successful tapeouts.
Block-Level Timing: Managed block-level Reg2Reg timing for two different hard macros, correlated block-level constraints with SoC-level constraints, conducted crosstalk analysis and TDRC reviews, tuned clocks at the block level for internal Reg2Reg paths, and generated timing ECOs for Reg2Reg paths. Collaborated closely with the SoC team for interface timing paths to achieve block closure.
SoC-Level Timing: Analyzed timing paths at the SoC level, including both Reg2Reg and interface paths for four different hard macros. Correlated SoC and hard macro level constraints, identified constraint issues such as case analysis on mux and undefined clocks on ports during the project’s initial phase, managed pipeline insertions, IO budgeting, and clock tuning for difficult timing path groups to achieve skew balancing. Manually generated ECOs for critical and sensitive paths, conducted thorough analysis for min-max conflict paths across different corners, and performed crosstalk analysis and TDRC reviews.

Snapdragon 8 series5nm technology7nm technology10nm technologytiming analysisECO generation+4

Institute of silicon systems pvt. ltd.

Physical Design Trainee

Jan 2017 – Sep 2017 · 8 mos · Hyderabad Area, India

Trained in VLSI Physical Design from Institute of Silicon Systems Pvt. Ltd., Hyderabad from January 2017 to June 2017 using Cadence Tools
Experience of working on Physical Design flow from Netlist to GDS II.
Good understanding of Physical design flow - Floor Planning, Power planning , Clock Tree Synthesis, Placement and Routing, block level timing enclosure, Crosstalk analysis, Qualitative R and C extraction, IR drop analysis, Logical Equivalence Check, Physical verification (DRC, LVS), Static Timing Analysis, Power optimization techniques, Antenna effect .
Cadence Tools:
SoC Encounter – Floor Planning, Power Planning, Placement, CTS, Routing and Sign-off.
Encounter Timing System – Sign-off Timing Enclosure
RTL Compiler – Logic Synthesis
Virtuoso Layout Editor – Layout Designing
Assura – Physical Verification
Scripting Language: TCL

Physical Design flowGDS IIFloor PlanningPower PlanningClock Tree SynthesisStatic Timing Analysis+2

Semiconductor labratory, department of space (isro)

Physical Design Trainee

Jul 2015 – Jun 2016 · 11 mos · Chandigarh, India

Completed a 1-year internship program at the Semi-Conductor Laboratory, Department of Space, Government of India, focusing on the “Indigenous Development of Radiation-Hardened Phase-Locked Loop for Space Applications.”
Designed radiation-hardened Phase-Locked Loops (PLLs) with components engineered for radiation tolerance, ensuring accurate and robust high-frequency clock generation in space applications.
Implemented strategies to mitigate Single Event Upsets (SEU) and Single Event Transients (SET) for PLL components, adopting a comprehensive approach to correct radiation-induced errors.
Enhanced radiation tolerance using Triple Modular Redundancy (TMR) design.

Radiation-Hardened PLLsSingle Event UpsetsTriple Modular RedundancyRadiation-Hardened Design