Devang Mahesh

Software Engineer

Austin, Texas, United States5 yrs experience

AI EnabledAI ML Practitioner

Key Highlights

Expert in CPU design and microarchitecture.
Proficient in RTL development and verification.
Experience with FPGA and ASIC systems.

Stackforce AI infers this person is a Semiconductor and Data Engineering specialist with strong RTL and CPU design expertise.

Contact

Skills

Core Skills

Cpu DesignMicroarchitectureRtl DevelopmentDigital Circuit DesignData Science

Other Skills

Artificial Intelligence (AI)C++Cadence VirtuosoChipscopeCocotbDeep LearningDigital ElectronicsElasticsearchEthicsGraylogHardware ArchitectureJavaLeadershipPower OptimizationPyTorch

About

A professional with experience in FPGA and ASIC systems, writing RTL for multiple designs and verifying them using simulations with coverage analysis. PPA optimization of CPU RTL.

Experience

Qualcomm

CPU Engineer

Jun 2025 – Present · 9 mos · Santa Clara, California, United States

Vector Execution Unit design at Nuvia.

CPU designMicroarchitecture

Mediatek

CPU RTL Intern

May 2024 – Aug 2024 · 3 mos · Austin, Texas Metropolitan Area · On-site

Worked on ZEBU emulation platform to extract PMU/AMU counters for in-depth PPA analysis of Middle CPU.

ZebuCPU designPower Optimization

The university of texas at austin

Graduate Teaching Assistant

Aug 2023 – May 2025 · 1 yr 9 mos

Apt portfolio private limited

Hardware Engineer

Jun 2021 – May 2023 · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

Worked on Xilinx Ultrascale+ FPGAs. Designs took in UDP feed from QSFP ports and generated TCP orders.
Designed and implemented the RTL for various computation modules and encryption blocks.

CocotbRTL DevelopmentScriptingSystemVerilogVerilatorWireshark+3

Indian institute of technology, delhi

2 roles

Undergraduate Teaching Assistant

Sep 2020 – Jan 2021 · 4 mos

Teaching assistant for the course Digital Electronics, ELL201

Undergrad. Research Assistant: NVM Group

Mar 2019 – Mar 2021 · 2 yrs

A.p.t. portfolio private limited

Hardware Intern

Apr 2020 – Jun 2020 · 2 mos · Bengaluru, Karnataka

Set up the Graylog pipeline to collect and visualize logs from FPGA servers. Used Filebeat to send logs to the Graylog server, Logstash to ingest data from multiple servers, and Elasticsearch to store data for faster retrieval.
Successfully automated dashboard creation using Python and Graylog’s REST API to visualize logs.

Python (Programming Language)REST APIsGraylogElasticsearch