Sarthi Chugh

Software Engineer

Noida, Uttar Pradesh, India6 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 6 years of experience in IP RTL design.
  • Expertise in SystemVerilog and RTL optimization.
  • Involvement in Functional Safety HW design.
Stackforce AI infers this person is a Hardware Design Engineer specializing in RTL and Functional Safety in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignPerformance OptimizationDebugTiming ProfilingLow-power Verification

Other Skills

Secure and Alias registersFast configuration restore logicParity checking logicHamming state encodingError Syndrome debugBoot optimizationLatency optimizationCoverage exclusions signoffConnectivity ReviewAutomationConfigurable secure registersAHB protocol slaveLintCDCDynamic power optimization

About

Contributing to IP RTL design since last 6+ years.Forte is System verilog based RTL design, code analysis and debug. Feature and CSRs Documentation, programming sequences, etc.Opportunistic involvement in Functional Safety HW design, Safety documents related to systematic development process.

Experience

Qualcomm

5 roles

Staff Engineer

Promoted

Dec 2025 – Present · 3 mos

Senior Lead Engineer

Dec 2022 – Nov 2025 · 2 yrs 11 mos

  • RTL Design using Secure and Alias registers
  • Fast configuration restore logic
  • Parity checking logic, Hamming state encoding
  • Error Syndrome debug, debug using debug registers
  • Boot, Performance and latency optimization
  • Coverage exclusions signoff
  • Connectivity Review
  • Automation
RTL DesignSecure and Alias registersFast configuration restore logicParity checking logicHamming state encodingError Syndrome debug+6

Senior Engineer

Promoted

Dec 2020 – Nov 2022 · 1 yr 11 mos

  • RTL design and debug
  • Design of configurable secure registers
  • Design of AHB protocol slave
  • Lint, CDC
  • Boot-performance and latency optimization
  • Dynamic power optimization
  • Automation
RTL designDebugConfigurable secure registersAHB protocol slaveLintCDC+3

Engineer

Jul 2019 – Nov 2020 · 1 yr 4 mos

  • Parametrized RTL design
  • Lint, CDC
  • Area & Timing profiling
  • Assertion & functional coverage coding
Parametrized RTL designLintCDCArea profilingTiming profilingAssertion coding+2

Interim Engineering Intern

Jan 2019 – Jun 2019 · 5 mos

  • Design conversion to parametrized RTL
  • Formal LEC
  • UPF parameterization, low-power verification
Parametrized RTL designFormal LECUPF parameterizationLow-power verificationRTL Design

Innostax software labs

Associate Software Developer

Apr 2016 – Jul 2016 · 3 mos · Gurugram, Haryana, India · On-site

Tata consultancy services

Asst. System Engineer Trainee

Nov 2015 – Feb 2016 · 3 mos · Gurugram, Haryana, India · On-site

Education

Birla Institute of Technology and Science, Pilani

Master of Engineering - MEng — Embedded Systems

Jan 2017 – Jan 2019

Ambedkar Institute of Advanced Communication Technologies and Research

Bachelor of Technology (B.Tech.)

Jan 2011 – Jan 2015

Stackforce found 100+ more professionals with Rtl Design & Performance Optimization

Explore similar profiles based on matching skills and experience

Arunava Saha

Arunava Saha

Senior Director, R&D

at Synopsys Inc

Dublin, United States19 yrs 9 mos exp
AIAI/MLComputer VisionLeadershipMachine Learning
Hari Babu Chimakurthy

Hari Babu Chimakurthy

Digital Design Manager

at Texas Instruments

Bengaluru, India13 yrs 8 mos exp
ADASASIC RTL DesignDRAM Memory DesignLow Power DesignMemory Interface Design
Dibakar Barua

Dibakar Barua

ASIC Engineer, Architecture

at Meta

San Francisco, United States10 yrs 6 mos exp
Deep LearningDesign VerificationFPGA PrototypingHardware-Software DesignLogic Design
ANIRUDH THANDRA

ANIRUDH THANDRA

Senior Staff Engineer

at Qualcomm

Mougins, France11 yrs exp
Hardware EmulationVerification and Validation (V&V)
Shwetang Singh

Shwetang Singh

Software Engineer

at Google

Hyderabad, India9 yrs 9 mos exp
5G Devices5G Protocol StackDebuggingEmbedded SystemsMulticore Real Time OS
Naveen Srivastava

Naveen Srivastava

Principal Architect

at Samsung Electronics

Bengaluru, India17 yrs 8 mos exp
ASIC ArchitectureImaging HW DesignSoC Power AnalysisMicroarchitectureRTL Design
Abhishek Jain

Abhishek Jain

Principal Architect

at Siemens EDA (Siemens Digital Industries Software)

Noida, India23 yrs 7 mos exp
Co-simulation toolEDAEmulationFunctional verification
Sai Teja Ch

Sai Teja Ch

Senior Engineer (Level 2) - Emulation

at eInfochips (An Arrow Company)

Hyderabad, India8 yrs 10 mos exp
EmulationPre silicon validation