Suman Bhat R — Software Engineer
8+ Years of Experience in VLSI Design Verification: - SoC Verification - RTL and Gate Level Simulation - Silicon Bringup Specialties: - System Verilog - OOPs Concepts, Assertion, Functional Coverage - Methodologies - UVM - AMBA - APB, AHB,AXI
Stackforce AI infers this person is a VLSI Design Verification Engineer with extensive experience in semiconductor technology.
Location: Bengaluru, Karnataka, India
Experience: 13 yrs 4 mos
Skills
- Vlsi Design Verification
- System Verilog
- Soc Verification
- Functional Verification
- Silicon Bringup
Career Highlights
- Over 8 years of experience in VLSI Design Verification.
- Expertise in SoC Verification and Silicon Bringup.
- Proficient in System Verilog and UVM methodologies.
Work Experience
Intel Corporation
Design Verification Engineer (3 yrs 9 mos)
Qualcomm
Design Verification Engineer (5 yrs 10 mos)
Tata Consultancy Services
Design Verification Engineer (3 yrs 9 mos)
Education
Bachelor of Engineering (BE) at Malnad College Of Engineering
