Chidambar A G — Software Engineer
• Hands-on experience in building UVM test bench from scratch using System Verilog. • Proficient in writing Test cases, Simulation and Debugging. • Experience in building test bench, creating BFMs using VHDL and Verilog. • Experience on SVA. • Experience in RTL design using VHDL & Verilog. • Experience on I2C, SPI, SGMII, Ethernet, ARINC, AXI, AHB, APB protocols. • Also have protocol knowledge on Xilinx CPRI/eCPRI platform. • Good knowledge on Python & Perl scripting. • Experience on DO-254 standards.
Stackforce AI infers this person is a Design Verification Engineer with expertise in VLSI and digital design.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 3 mos
Skills
- Uvm
- Rtl Design
Career Highlights
- Expert in UVM and RTL design methodologies.
- Hands-on experience with multiple communication protocols.
- Proficient in both VHDL and Verilog for test bench creation.
Work Experience
Qualcomm
Senior Engineer (3 yrs 9 mos)
Cerium Systems
Engineer (1 yr 2 mos)
Altran
SoC Verification Engineer (1 yr 7 mos)
Design Verification Engineer (3 yrs 1 mo)
Maven Silicon
Internship (1 mo)
Trainee (3 mos)
Education
Bachelor of Technology - BTech at Jain (Deemed-to-be University)
