Surabhi Misra — Co-Founder
ASIC Design Engineer at Cisco working on networking ASICs and communication processors. My work centers on micro-architecture, RTL design, and frameworks. I hold a Master’s degree in Electrical Engineering from the University of Southern California, where I worked on logic locking, NoC architecture, and memory systems. I’m particularly interested in hardware security and in simplifying complex hardware concepts through writing, diagrams, and technical talks. I enjoy sharing insights with the ASIC and chip design community and contributing to conversations around building secure, reliable silicon. If you’d like to have a structured 1:1 conversation around RTL design, microarchitecture, or hardware security, you can book time here: https://topmate.io/surabhi_misra/
Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on ASIC and hardware security.
Location: San Jose, California, United States
Experience: 2 yrs 8 mos
Skills
- Asic Design
- Rtl Design
- Chip Design
- Circuit Evaluation
- Content Management
- Processor Design
Career Highlights
- Expertise in ASIC design and micro-architecture.
- Strong background in hardware security and RTL design.
- Passionate about community engagement in chip design.
Work Experience
topmate.io
Mentor (2 mos)
Cisco
ASIC Design Engineer II (5 mos)
ASIC Design Engineer I (2 yrs 3 mos)
ASIC Engineer (4 mos)
Intel Corporation
Component Design Intern (5 mos)
USC Viterbi K-12 STEM Center
Student Communications Coordinator - Webmaster (5 mos)
Maven Silicon
Digital Design Intern (2 mos)
Hindustan Shipyard Limited - India
Internship Trainee (1 mo)
Ecil(Electronics Corporation Of India Limited)
Summer Internship (1 mo)
Education
Master's degree at University of Southern California
