Meghana G

Software Engineer

Bengaluru, Karnataka, India1 yr 11 mos experience
Most Likely To Switch

Key Highlights

  • Trained in Physical Design VLSI.
  • Hands-on experience with STA and placement.
  • Currently working as an Associate Engineer.
Stackforce AI infers this person is a VLSI Design Engineer with a focus on Physical Design.

Contact

LinkedIn

Skills

Other Skills

placementSTAPlace & RoutepowerplanClock Tree SynthesisRoutingFloorplanning

About

Professional trained on Physical Design VLSI

Experience

1 yr 11 mos
Total Experience
11 mos
Average Tenure
1 yr 6 mos
Current Experience

Astrasilica technologies private ltd

Associate Engineer

Oct 2024 – Present · 1 yr 6 mos · Bengaluru, Karnataka, India · On-site

Takshila institute of vlsi technologies

2 roles

Physical Design

Oct 2023 – Mar 2024 · 5 mos

Trained Physical Design Engineer

Oct 2023 – Feb 2024 · 4 mos

placementSTA

Education

AMC Engineering College - India

B.Tech — Electronics and communication engineering

Aug 2019 – Jun 2023

Takshila VLSI Training Institute in Bangalore

Oct 2023 – Feb 2024

Takshila VLSI Training Institute in Bangalore

Takshila VLSI Training Institute in Bangalore

Takshila VLSI Training Institute in Bangalore

Stackforce found 100+ more professionals with placement & STA

Explore similar profiles based on matching skills and experience

Surendranath Reddy

Surendranath Reddy

Design Automation Engineer

at Intel India Technology Pvt Ltd

Bengaluru, India15 yrs 9 mos exp
Physical DesignVLSIDesign Automation
MV

Mohith Varma

ASIC Physical Design Engineer

at Sumedha Institute of Technology

Hyderabad, India0 mo exp
Physical DesignStatic Timing Analysis
Jeevan K Y

Jeevan K Y

Senior SOC Design Engineer

at Intel Corporation

Bengaluru, India8 yrs 7 mos exp
Physical DesignLEC
Thejasvi N

Thejasvi N

Graphics hardware engineer

at Intel Corporation

India6 yrs 10 mos exp
Physical DesignClockingCAD Automation
RV

raghu venegalla

Senior Lead Engineer

at Qualcomm

Karnataka, India14 yrs 9 mos exp
Physical DesignStatic Timing Analysis
Naveen Silveri

Naveen Silveri

Staff Engineer

at MediaTek

Bengaluru, India14 yrs 4 mos exp
ASIC Design FlowPhysical Design
UD

Uday Dasari

Sr. Engineering Manager

at Google

Santa Clara, United States18 yrs exp
Low Power SystemsPhysical DesignSystem on a Chip (SoC)
Anusha C V

Anusha C V

Physical Design Engineer

at Capgemini Engineering

Bengaluru, India4 yrs 7 mos exp
Integrated Circuits (IC)Physical Design