Arjun Singh

Software Engineer

Delhi, India9 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in DFT methodologies and Scan Insertion.
Proficient in scripting for workflow automation.
Strong background in VLSI and Embedded Systems.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in DFT and automation.

Contact

Skills

Core Skills

DftScan InsertionAtpg

Other Skills

Automatic Test Pattern Generation (ATPG)Gate Level SimulationPerlTetramaxDFT CompilerCadence XceliumVerilogCSemiconductorsVLSISystemCMicrocontrollersC++MatlabVHDL

About

Graduate in VLSI and Embedded Systems from Indraprastha Institute of Information Technology, New Delhi, with a strong passion for the VLSI industry. Currently focused on building a career as a Design Engineer in the DFT (Design for Testability) domain. Experienced in Scan Insertion using Fusion Compiler and Genus, and proficient in ATPG methodologies. Possess deep knowledge of DFT features such as wrapper cell working, IEEE 1149.1 (JTAG), and IEEE 1687 (IJTAG). Skilled in scripting with Perl, TCL, and Shell, enabling workflow automation and process optimization. Passionate about solving complex design challenges and staying at the forefront of advancements in semiconductor technology. Open to connecting with professionals in the VLSI industry to exchange ideas, collaborate, and explore new opportunities.

Experience

9 yrs 7 mos

Total Experience

2 yrs 9 mos

Average Tenure

1 yr 4 mos

Current Experience

Qualcomm

Senior Lead Engineer

Dec 2024 – Present · 1 yr 4 mos · Noida, Uttar Pradesh, India · On-site

Nxp semiconductors

2 roles

Technical Lead

Apr 2023 – Dec 2024 · 1 yr 8 mos · Noida, Uttar Pradesh, India · On-site

Lead Scan Insertion script development, spyglass, and various tool and flow enhancement on multiple projects.

Senior Design Engineer

Dec 2020 – Apr 2023 · 2 yrs 4 mos · Noida, Uttar Pradesh, India · On-site

1. Started my work with GLS on Transition Fault patterns for both Zero-Delay and Timing.
2. Worked on XLS based flow development for Scan Insertion on Synopsys FC.
3. Working on scan insertion on various hard macros and subsystem levels and fixing issues related to tool limitation, design changes etc.
4. Working on ATPG on subsystem level and retargetting.

Automatic Test Pattern Generation (ATPG)Gate Level SimulationScan InsertionDFT

Stmicroelectronics

2 roles

Design Engineer

Jun 2018 – Dec 2020 · 2 yrs 6 mos · Noida Area, India

1. Worked on ATPG to generate patterns using Mentor Graphics Tessent Testkompress. And simulate them on Cadence Incisive tool.
2. Automated a setup environment for regression which uses Cadence Xcelium to reduce compilation and elaboration time of netlist for every testbench simulation. Now only one compilation and elaboration of netlist is required and every testbench in regression uses the same database to simulate patterns. For setup and automation I used perl and shell scripting.
3. Worked on Scan Insertion on Hard Macro level on Synopsys DC and enabled various features like Scan Compression, Test Point insertion, Core Wrapping etc.
4. Enabled SHS based solution for running LBIST using in-house JTAG Machine.

PerlTetramaxDFT CompilerATPGScan Insertion

Graduate Intern

May 2017 – May 2018 · 1 yr · Noida Area, India

Worked in DFT Team on LBIST and ATPG.
1. STUCKAT, ATSPEED and BurnIn pattern generations for SOC using Mentor Graphics Tessent TestKompress. Simulating Patterns using Cadence Incisive Enterprise Manager. Debugging SOC on circuit level.
2. LBIST Simulation

Indraprastha institute of information technology, delhi

Teaching Assistant

Aug 2016 – May 2017 · 9 mos · New Delhi Area, India

I was Teaching Assistant for Embedded Logic Design during Aug, 2016 - Nov, 2016 and for Introduction to Engineering Design during Jan, 2017 - April, 2017.